Axi Control Signals In The Processor; Figure 8-2 Channel Architecture Of Reads; Figure 8-3 Channel Architecture Of Writes - ARM ARM1176JZF-S Technical Reference Manual

8.3

AXI control signals in the processor

ARM DDI 0301H
ID012310
This section describes the processor implementation of the AXI control signals:
For additional information about AXI, see the AMBA AXI Protocol Specification.
The AXI protocol is burst-based. Every transaction has address and control information on the
address channel that describes the nature of the data to be transferred. The data is transferred
between master and slave using a write channel to the slave or a read channel to the master. In
write transactions, where all the data flows from the master to the slave, the AXI has an
additional write response channel to enable the slave to signal to the master the completion of
the write transaction.
The AXI protocol permits address information to be issued ahead of the actual data transfer and
enables support for multiple outstanding transactions in addition to out-of-order completion of
transactions.
Figure 8-2 shows how a read transaction uses the read address and read data channels.
Master
interface
Figure 8-3 shows how a write transaction uses the write address, write data, and write response
channels.
Master
interface
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Read address channel
Address
and
control
Read channel
Read Read
data data

Figure 8-2 Channel architecture of reads

Write address channel
Address
and
control
Write channel
Write Write
data data
Write response channel

Figure 8-3 Channel architecture of writes

Level Two Interface
Read Read
data data
Write Write
data data
Write
response
Slave
interface
Slave
interface
8-8