ARM ARM1176JZF-S Technical Reference Manual page 48

ARM DDI 0301H
ID012310
• access to slow areas of memory marked as Device or Strongly Ordered must not be
performed. That is, those that take many cycles in generating a response
• SWP operations must not be performed to slow areas of memory.
Configuration
You configure the processor for low interrupt latency mode by use of the system control
coprocessor. To ensure that a change between normal and low interrupt latency configurations
is synchronized correctly, you must use software systems that only change the configuration
while interrupts are disabled.
Exception processing enhancements
The ARMv6 architecture contains several enhancements to exception processing, to reduce
interrupt handler entry and exit time:
SRS Save return state to a specified stack frame.
RFE Return from exception.
CPS Directly modify the CPSR.
Note
With TrustZone, in Non-secure state, specifying Secure Monitor mode in the
SRS instruction causes the processor to take the Undefined exception.
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Introduction
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