Table B-3 Cp15 C15 Only Found In Arm1136Jf-S Processors - ARM ARM1176JZF-S Technical Reference Manual

B.2.12 DMA
ARM DDI 0301H
ID012310
Table B-3 lists the features that are implemented in the ARM1136JF-S processor but not in
ARM1176JZF-S processors.
CRn Opcode_1
c15 0
3
5
c15 5
7
a. In the ARM1136JF-S processor is possible to read and write all TLB entries. In ARM1176JZF-S
processor you can only read or write the lockdown entries.
The ARM1176JZF-S processor transfers all data as part of the DMA transfer from TCM to
external memory. ARM1136JF-S processors only transfer dirty data at a granularity of four
words for the Data TCM.
The DMA in the ARM1176JZF-S processor now supports burst accesses in addition to single
accesses.
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Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences

Table B-3 CP15 c15 only found in ARM1136JF-S processors

CRm Opcode_2 Register Function
c2 0 Data Memory Remap Register
1 Instruction Memory Remap Register
2 DMA Memory Remap Register
C0 0 Data Debug Cache
1 Instruction Debug Cache
C2 0 Data TAG RAM Read Operation
1 Instruction TAG RAM Read Operation
C4 1 Instruction Cache RAM Data Read Operation
C4 0 Data MicroTLB Entry Operation
1 Instruction MicroTLB Entry Operation
2
Read Main TLB Entry
4
Write Main TLB Entry
C5 0 Data MicroTLB VA
1 Instruction MicroTLB VA
2
Main TLB VA
C6 0 Data MicroTLB PA
1 Instruction MicroTLB PA
2
Main TLB PA
C7 0 Data MicroTLB Attribute
1 Instruction MicroTLB Attribute
2
Main TLB Attribute
C14 Main TLB Valid
C0 0 Cache Debug Control
1 TLB Debug Control
a
a
a
a
a
B-9