Table of Contents
Advertisement
31
31
31
Coarse page table base address
31
Coarse page table base address
31
Page base address
31
Page base address
ARM DDI 0301H
ID012310
If the second level descriptor describes a large page, a small page, or an extended small page
when the Force AP bit is set and the MMU is in ARMv6 mode, Access bit faults might be
generated if AP[0]=0.
Second-level large page base address
If bits [1:0] of the second-level descriptor are b01, then a large page table walk is required.
Figure 6-14 shows the translation process for a 64KB large page using ARMv6 format, AP bits
disabled.
Translation table base
14 13
Translation base
First-level descriptor address
14 13
Translation base
First-level descriptor
Second-level descriptor address
Second-level descriptor
16 15
14
X
TEX
N
Physical address
16 15
Figure 6-15 on page 6-49 shows the translation process for a 64KB large page, or a 16KB large
page subpage, using backwards-compatible format, AP bits enabled.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Modified virtual address
31
20 19
First-level table index
2 1
First-level table index
0
10 9 8
5 4
3
2 1 0
N
P Domain
0
S
SBZ
10 9
2 1 0
Second-level
0
table index
12 11 10 9 8
6 5 4 3 2 1 0
A
n
S
SBZ AP C B 0
P
G
X
Page index
Figure 6-14 Large page table walk, ARMv6 format
Memory Management Unit
0
16 15
12 11
Page index
Second-level
table index
0
0
1
SBZ
0
1
0
0
6-48
Hide quick links:
Advertisement
Table of Contents
