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Chapter 16
Cycle Timings and Interlock Behavior
This chapter describes the cycle timings and interlock behavior of integer instructions on the
ARM1176JZF-S processor. This chapter contains the following sections:
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ARM DDI 0301H
ID012310
About cycle timings and interlock behavior on page 16-2
Register interlock examples on page 16-6
Data processing instructions on page 16-7
QADD, QDADD, QSUB, and QDSUB instructions on page 16-9
ARMv6 media data-processing on page 16-10
ARMv6 Sum of Absolute Differences (SAD) on page 16-11
Multiplies on page 16-12
Branches on page 16-14
Processor state updating instructions on page 16-15
Single load and store instructions on page 16-16
Load and Store Double instructions on page 16-19
Load and Store Multiple Instructions on page 16-21
RFE and SRS instructions on page 16-23
Synchronization instructions on page 16-24.
Coprocessor instructions on page 16-25
SVC, SMC, BKPT, Undefined, and Prefetch Aborted instructions on page 16-26
No operation on page 16-27
Thumb instructions on page 16-28.
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