Table of Contents
Advertisement
ARM DDI 0301H
ID012310
TrustZone extensions enable the system to mark each entry in the TLB as Secure or Non-secure
with the NSTID. At any time the processor only enables entries with an NSTID that matches the
Security state of the current application.
The set of memory properties associated with each TLB entry include:
Memory access permission control
This controls if a program has no-access, read-only access, or read/write access
to the memory area. When an access is attempted without the required
permission, a memory abort is signaled to the processor. The level of access
possible can also be affected by whether the program is running in User mode, or
a privileged mode, and by the use of domains. See Memory access control on
page 6-11 for more details.
Memory region attributes
These describe properties of a memory region. Examples include Strongly
Ordered, Device, cacheable Write-Through, and cacheable Write-Back. If an
entry for a virtual address is not found in a TLB then a set of translation tables in
memory are automatically searched by hardware to create a TLB entry. This
process is known as a translation table walk. If the processor is in ARMv5
backwards-compatible mode some new features, such as ASIDs, are not
available. The MMU architecture also enables specific TLB entries to be locked
down in a TLB. This ensures that accesses to the associated memory areas never
require looking up by a translation table walk. This minimizes the worst-case
access time to code and data for real-time routines.
Non-secure memory region attribute
This attribute is a TrustZone security extension to the existing ARMv6 MMU. It
defines when the target memory is Secure or Non-secure. See NS attribute on
page 6-19 for a detailed explanation of this bit.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Memory Management Unit
6-3
Hide quick links:
Advertisement
Table of Contents
