16.12 Load And Store Multiple Instructions; Table 16-18 Cycle Timing Behavior Of Load And Store Multiples, Other Than Load Multiples Including The Pc - ARM ARM1176JZF-S Technical Reference Manual

16.12 Load and Store Multiple Instructions

16.12.1 Load and Store Multiples, other than load multiples including the PC

Table 16-18 Cycle timing behavior of Load and Store Multiples, other than load multiples including the PC

Example Instruction
First address 64-bit aligned
LDMIA Rx,{R1}
LDMIA Rx,{R1,R2}
LDMIA Rx,{R1,R2,R3}
LDMIA Rx,{R1,R2,R3,R4}
LDMIA Rx,{R1,R2,R3,R4,R5}
LDMIA Rx,{R1,R2,R3,R4,R5,R6}
LDMIA Rx,{R1,R2,R3,R4,R5,R6,R7}
First address not 64-bit aligned
LDMIA Rx,{R1}
LDMIA Rx,{R1,R2}
LDMIA Rx,{R1,R2,R3}
LDMIA Rx,{R1,R2,R3,R4}
LDMIA Rx,{R1,R2,R3,R4,R5}
LDMIA Rx,{R1,R2,R3,R4,R5,R6}
LDMIA Rx,{R1,R2,R3,R4,R5,R6,R7}
ARM DDI 0301H
ID012310
This section describes the cycle timing behavior for the LDM and STM instructions.
These instructions take one cycle to issue but then use multiple memory cycles to load/store all
the registers. Because the memory datapath is 64-bits wide, two registers can be loaded or stored
on each cycle. Following non-dependent, non-memory instructions can execute in the integer
pipeline while these instructions complete. A dependent instruction is one that either:
• writes a register that has not yet been stored
• reads a register that has not yet been loaded.
Before a load or store multiple can begin, all the registers in the register list must be available.
For example, a STM cannot begin until all outstanding loads for registers in the register list have
completed.
To prevent instructions after a store multiple from writing to a register before a store multiple
has stored that register, the register list has a lock latency that determines how many cycles it is
before a subsequent instruction that writes to that register can start.
In all cases the base register, Rx, is an Early Reg.
Table 16-18 lists the cycle timing behavior of load and store multiples including the PC.
Cycle
s
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Memory Result latency
cycles (LDM)
1 3
1 3,3
2 3,3,4
2 3,3,4,4
3 3,3,4,4,5
3 3,3,4,4,5,5
4 3,3,4,4,5,5,6
1 3
2 3,4
2 3,4,4
3 3,4,4,5
3 3,4,4,5,5
4 3,4,4,5,5,6
4 3,4,4,5,5,6,6
Cycle Timings and Interlock Behavior
Register Lock Latency
(STM)
1
1,2
1,2,2
1,2,2,3
1,2,2,3,3
1,2,2,3,3,4
1,2,2,3,3,4,4
1
1,2
1,2,2
1,2,2,3
1,2,2,3,4
1,2,2,3,4,4
1,2,2,3,4,4,5
16-21