Table 10-4 Debug Exception And Monitor Control Register; Figure 10-3 Debug Exception And Monitor Control Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

31
Bits Type
[31:25] -
[24] Read/write
[23:20] -
[19] Read/write
[18] Read/write
ARM DDI 0337G
Unrestricted Access
25 24 23
SBZP SBZP
TRCENA MON_REQ
MON_STEP
MON_PEND
MON_EN

Figure 10-3 Debug Exception and Monitor Control Register bit assignments

Table 10-4 shows the bit functions of the Debug Exception and Monitor Control
Register.
Field Function
- Reserved, SBZP
TRCENA This bit must be set to 1 to enable use of the trace and debug blocks:
•
•
•
•
This enables control of power usage unless tracing is required. The
application can enable this, for ITM use, or use by a debugger.
If no debug or trace components are present in the implementation then
it is not possible to set TRCENA.
- Reserved, SBZP
a This enables the monitor to identify how it wakes up:
MON_REQ
1 = woken up by MON_PEND
0 = woken up by debug exception.
a When MON_EN = 1, this steps the core. When MON_EN = 0, this bit
MON_STEP
is ignored. This is the equivalent to C_STEP. Interrupts are only
stepped according to the priority of the monitor and settings of
PRIMASK, FAULTMASK, or BASEPRI.
Copyright © 2005-2008 ARM Limited. All rights reserved.
20 19 18 17 16 15
SBZP
VC_HARDERR
VC_INTERR
VC_BUSERR
VC_STATERR
VC_CHKERR
VC_NOCPERR
VC_MMERR
VC_CORERESET

Table 10-4 Debug Exception and Monitor Control Register

Data Watchpoint and Trace (DWT)
Instrumentation Trace Macrocell (ITM)
Embedded Trace Macrocell (ETM)
Trace Port Interface Unit (TPIU).
Note
Non-Confidential
11 10 9 8 7 6 5 4
Core Debug
3 1 0
SBZP
10-9