Table 3-95 Cache Behavior Override Register Bit Functions; Table 3-96 Results Of Access To The Cache Behavior Override Register - ARM ARM1176JZF-S Technical Reference Manual

Bits Field name
[31:6] -
[5] S_WT
[4] S_IL
[3] S_DL
[2] NS_WT
[1] NS_IL
[0] NS_DL
Bits
Secure only [5:3]
Common [2:0]
ARM DDI 0301H
ID012310
Table 3-95 lists how the bit values correspond to the Cache Behavior Override Register.
Access Function
- UNP/SBZ.
Secure only Defines write-through behavior for regions marked as Secure write-back:
0 = Do not force write-through, normal operation, reset value
1 = Force write-through.
Secure only Defines Instruction Cache linefill behavior for Secure regions:
0 = Instruction Cache linefill enabled, normal operation, reset value
1 = Instruction Cache linefill disabled.
Secure only Defines Data Cache linefill behavior for Secure regions:
0 = Data Cache linefill enabled, normal operation, reset value
1 = Data Cache linefill disabled.
Common Defines write-through behavior for regions marked as Non-secure write-back:
0 = Do not force write-through, normal operation, reset value
1 = Force write-through.
Common Defines Instruction Cache linefill behavior for Non-secure regions:
0 = Instruction Cache linefill enabled, normal operation, reset value
1 = Instruction Cache linefill disabled.
Common Defines Data Cache linefill behavior for Non-secure regions:
0 = Data Cache linefill enabled, normal operation, reset value
1 = Data Cache linefill disabled.
Table 3-96 lists the actions that result from attempted access for each mode.

Table 3-96 Results of access to the Cache Behavior Override Register

Secure Privileged access
Data
Data
To use the Cache Behavior Override Register read or write CP15 with:
• Opcode_1 to 0
• CRn set to c9
• CRm set to c8
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c9, c8, 0
MCR p15, 0, <Rd>, c9, c8, 0
You might use the Cache Behavior Override Register during, for example, clean or clean and
invalidate all operations in Non-secure world that might not prevent fast interrupts to the Secure
world if the FW bit is clear, see c1, Secure Configuration Register on page 3-52. In this case, the
Secure world can read or write the Non-secure locations in the cache, so potentially causing the
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Table 3-95 Cache Behavior Override Register bit functions

Non-secure Privileged access
Read
Read As Zero
Data
; Read Cache Behavior Override Register
; Write Cache Behavior Override Register
System Control Coprocessor
User access
Write
Ignored Undefined exception
Data Undefined exception
3-98