Page 2: Change History
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 3: Table Of Contents
Data types ....................2-6 Operating modes ..................2-7 Registers ..................... 2-8 The program status registers ..............2-13 Exceptions ....................2-16 Interrupt latencies ..................2-23 2.10 Reset ......................2-24 ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 4 Load multiple registers ................6-15 6.10 Store multiple registers ................6-17 6.11 Data swap ....................6-18 6.12 Software interrupt and exception entry ............. 6-19 6.13 Coprocessor data operation ..............6-20 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 5 Differences Between Rev 3a and Rev 4 Summary of differences between Rev 3a and Rev 4 ......... C-2 Detailed descriptions of differences between Rev 3a and Rev 4 ....C-3 Glossary ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 7 Read accesses ......................3-27 Table 3-8 Use of nM[4:0] to indicate current processor mode ..........3-31 Table 4-1 Coprocessor availability .................... 4-3 Table 4-2 Handshaking signals ....................4-6 ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 8 Table 7-19 Reset period timing parameters ................7-17 Table 7-20 Output enable and disable timing parameters ............7-18 Table 7-21 ALE address control timing parameters ..............7-19 viii Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 9 MAS[1:0] signal encoding ..................B-45 Table B-7 Debug control register bit assignments ..............B-51 Table B-8 Interrupt signal control ..................... B-52 Table B-9 Debug status register bit assignments ..............B-54 ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 11 Register organization in ARM state ................2-9 Figure 2-4 Register organization in Thumb state ..............2-10 Figure 2-5 Mapping of Thumb-state registers onto ARM-state registers ........2-11 Figure 2-6 Program status register format ................2-13 Figure 3-1 Simple memory cycle ....................3-4 Figure 3-2 Nonsequential memory cycle ..................
Page 12 Output enable and disable times due to HIGHZ TAP instruction ......7-17 Figure 7-21 Output enable and disable times due to data scanning .......... 7-18 Figure 7-22 ALE address control ....................7-18 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 13 Debug control register format .................. B-51 Figure B-10 Debug status register format ................... B-54 Figure B-11 Debug control and status register structure ............B-55 Figure B-12 Debug abort status register ..................B-56 ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. xiii...
Page 15 Preface This preface introduces the ARM7TDMI r4p1 Technical Reference Manual. It contains the following sections: • About this manual on page xvi • Feedback on page xx. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 16: Preface
About this manual This is the ARM for the ARM7TDMI r4p1 processor. Product revision status The rnpn identifier indicates the revision status of the product described in this ARM, where: Identifies the major revision of the product. Identifies the minor revision or modification status of the product.
Page 17 Read this chapter for a description of the AC and DC parameters, timing diagrams, definitions, and operating data. Appendix A Signal and Transistor Descriptions Read this chapter for a description of the ARM7TDMI core signals. Appendix B Debug in Depth Read this chapter for further information on the debug interface and EmbeddedICE-RT macrocell.
Page 18: Key To Timing Diagram Conventions
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means HIGH for active-HIGH signals and LOW for active-LOW signals. Prefix H Denotes Advanced High-performance Bus (AHB) signals. xviii Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 19 ARM Limited http://www.arm.com Frequently Asked Questions list. ARM publications This document contains information that is specific to the ARM7TDMI core. See the following documents for other relevant information: • ARM Architecture Reference Manual (ARM DDI 0100).
Page 20: Feedback
Preface Feedback ARM Limited welcomes feedback both on the ARM7TDMI r4p1 processor, and its documentation. Feedback on this product If you have any comments or suggestions about this product, please contact your supplier giving: • the product name • a concise explanation of your comments.
Page 21 Chapter 1 Introduction This chapter introduces the ARM7TDMI r4p1 processor. It contains the following sections: • About the ARM7TDMI core on page 1-2 • Architecture on page 1-5 • Block, core, and functional diagrams on page 1-7 • Instruction set summary on page 1-11.
Page 22: Chapter 1 Introduction
EmbeddedICE-RT logic on page 1-3. 1.1.1 The instruction pipeline The ARM7TDMI core uses a pipeline to increase the speed of the flow of instructions to the processor. This enables several operations to take place simultaneously, and the processing and memory systems to operate continuously.
Page 23: Memory Access
1.1.2 Memory access The ARM7TDMI core has a Von Neumann architecture, with a single 32-bit data bus carrying both instructions and data. Only load, store, and swap instructions can access data from memory.
Page 24 Introduction For more information about the EmbeddedICE-RT logic, see Chapter 5 Debug Interface and Appendix B Debug in Depth. Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 25: Architecture
1.2.2 The Thumb instruction set The Thumb instruction set is a subset of the most commonly used 32-bit ARM instructions. Thumb instructions are each 16 bits long, and have a corresponding 32-bit ARM instruction that has the same effect on the processor model. Thumb instructions operate with the standard ARM register configuration, allowing excellent interoperability between ARM and Thumb states.
Page 26 Thumb therefore offers a long branch range, powerful arithmetic operations, and a large address space. Thumb code is typically 65% of the size of ARM code, and provides 160% of the performance of ARM code when running from a 16-bit memory system. Thumb, therefore, makes the ARM7TDMI core ideally suited to embedded applications with restricted memory bandwidth, where code density and footprint is important.
Page 27: Block, Core, And Functional Diagrams
The ARM7TDMI processor architecture, core, and functional diagrams are illustrated in the following figures: • Figure 1-2 on page 1-8 shows a block diagram of the ARM7TDMI processor components and major signal paths • Figure 1-3 on page 1-9 shows the main processor logic at the core of the ARM7TDMI •...
Page 28: Figure 1-2 Arm7Tdmi Processor Block Diagram
EXTERN0 EXTERN1 nOPC MAS[1:0] All other nTRANS signals nMREQ ARM7TDM A[31:0] (CPU core) D[31:0] DIN[31:0] DOUT[31:0] SCREG[3:0] TAP controller IR[3:0] TAPSM[3:0] nTRST Figure 1-2 ARM7TDMI processor block diagram Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 29: Figure 1-3 Arm7Tdmi Main Processor Logic
Barrel shifter LOCK nCPI nM[4:0] 32-bit ALU TBIT HIGHZ Instruction pipeline Write data register Read data register Thumb instruction controller nENOUT nENIN D[31:0] Figure 1-3 ARM7TDMI main processor logic ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 30: Figure 1-4 Arm7Tdmi Processor Functional Diagram
EXTERN1 Memory nTRANS management EXTERN0 ABORT interface Debug DBGEN RANGEOUT0 Power RANGEOUT1 nOPC DBGRQI Coprocessor nCPI COMMRX interface COMMTX INSTRVALID Figure 1-4 ARM7TDMI processor functional diagram 1-10 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 31: Instruction Set Summary
Introduction Instruction set summary This section provides a description of the instruction sets used on the ARM7TDMI processor. This section describes: • Format summary • ARM instruction summary on page 1-13 • Thumb instruction summary on page 1-20. 1.4.1 Format summary This section provides a summary of the ARM, and Thumb instruction sets: •...
Page 32: Operand 2
Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for instance a multiply instruction with bit [6] changed to a 1. These instructions must not be used because their action might change in future ARM implementations. The behavior of these instruction codes on the ARM7TDMI processor is unpredictable.
Page 33: Table 1-2 Arm Instruction Summary
Introduction 1.4.2 ARM instruction summary The ARM instruction set summary is listed in Table 1-2. Table 1-2 ARM instruction summary Operation Assembly syntax Move Move MOV{cond}{S} Rd, <Oprnd2> Move NOT MVN{cond}{S} Rd, <Oprnd2> Move SPSR to register MRS{cond} Rd, SPSR...
Page 34 Stack operation, and restore CPSR LDM{cond}<a_mode4L> Rd{!}, <reglist+pc>^ • Stack operation with user registers LDM{cond}<a_mode4L> Rd{!}, <reglist>^ Store Word STR{cond} Rd, <a_mode2> Word with user-mode privilege STR{cond}T Rd, <a_mode2P> 1-14 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 35 Software interrupt SWI 24bit_Imm Addressing modes The addressing modes are procedures shared by different instructions for generating values used by the instructions. The five addressing modes used by the ARM7TDMI processor are: Mode 1 Shifter operands for data processing instructions.
Page 36: Table 1-3 Addressing Modes
Immediate [Rn], #+/-12bit_Offset Register [Rn], +/-Rm Scaled register [Rn], +/-Rm, LSL #5bit_shift_imm [Rn], +/-Rm, LSR #5bit_shift_imm [Rn], +/-Rm, ASR #5bit_shift_imm [Rn], +/-Rm, ROR #5bit_shift_imm [Rn, +/-Rm, RRX] 1-16 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 37 [Rn, +/-Rm]! Post-indexed [Rn], +/-Rm Mode 4, load <a_mode4L> IA, increment after FD, full descending IB, increment before ED, empty descending DA, decrement after FA, full ascending ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 1-17...
Page 38 Logical shift left Rm LSL Rs Logical shift right Rm LSR Rs Arithmetic shift right Rm ASR Rs Rotate right Rm ROR Rs Rotate right extended Rm RRX 1-18 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 39: Table 1-5 Fields
Greater, or equal N=V (N and V set or N and V clear) Less than N<>V (N set and V clear) or (N clear and V set) ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 1-19...
Page 40 1.4.3 Thumb instruction summary The Thumb instruction set formats are shown in Figure 1-6 on page 1-21. See the ARM Architectural Reference Manual for more information about the ARM instruction set formats. 1-20 Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 41: Figure 1-6 Thumb Instruction Set Formats
1 1 1 Offset Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 1-6 Thumb instruction set formats ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 1-21...
Page 42: Table 1-7 Thumb Instruction Set Summary
Compare High, and Low CMP Hd, Rs Compare High, and High CMP Hd, Hs Compare Negative CMN Rd, Rs Compare Immediate CMP Rd, #8bit_Imm Logical AND Rd, Rs 1-22 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 43 (Z clear and ((N or V set) or (N or V clear))) BGT label • if (Z set or ((N set and V clear) or (N clear and BLE label V set))) ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 1-23...
Page 44 ADD Rd, SP, #10bit_Offset Multiple LDMIA Rb!, <reglist> Store With immediate offset • word STR Rd, [Rb, #7bit_offset] • halfword STRH Rd, [Rb, #6bit_offset] • byte STRB Rd, [Rb, #5bit_offset] 1-24 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 45 Push LR, and registers onto stack PUSH <reglist, LR> Pop registers from stack POP <reglist> Pop registers, and pc from stack POP <reglist, PC> Software Interrupt SWI 8bit_Imm ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 1-25...
Page 47 Chapter 2 Programmer’s Model This chapter describes the ARM7TDMI core programmer’s model. It contains the following sections: • About the programmer’s model on page 2-2 • Processor operating states on page 2-3 • Memory formats on page 2-4 • Data types on page 2-6 •...
Page 48: Chapter 2 Programmer's Model
About the programmer’s model The ARM7TDMI processor core implements ARM architecture v4T, which includes the 32-bit ARM instruction set, and the 16-bit Thumb instruction set. The programmer’s model is described in the ARM Architecture Reference Manual. Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 49: Processor Operating States
2.2.1 Switching state The operating state of the ARM7TDMI core can be switched between ARM state and Thumb state using the BX instruction. This is described in the ARM Architecture Reference Manual. All exception handling is entered in ARM state. If an exception occurs in Thumb state, the processor reverts to ARM state.
Page 50: Memory Formats
For example: • bytes zero to three hold the first stored word • bytes four to seven hold the second stored word. The ARM7TDMI processor is bi-endian and can treat words in memory as being stored in either: • Little-endian. •...
Page 51: Figure 2-2 Big-Endian Addresses Of Bytes And Halfwords Within Words
2.3.2 Big-endian In big-endian format, the ARM7TDMI processor stores the most significant byte of a word at the lowest-numbered byte, and the least significant byte at the highest-numbered byte. So the byte at address 0 of the memory system connects to data lines 31 through 24.
Page 52: Data Types
Programmer’s Model Data types The ARM7TDMI processor supports the following data types: • words, 32-bit • halfwords, 16-bit • bytes, 8-bit. You must align these as follows: • word quantities must be aligned to four-byte boundaries • halfword quantities must be aligned to two-byte boundaries •...
Page 53: Operating Modes
Operating modes The ARM7TDMI processor has seven modes of operation: • User mode is the usual ARM program execution state, and is used for executing most application programs. • Fast Interrupt (FIQ) mode supports a data transfer or channel process.
Page 54: Registers
2.6.1 The ARM-state register set In ARM state, 16 general registers and one or two status registers are accessible at any one time. In privileged modes, mode-specific banked registers become available. Figure 2-3 on page 2-10 shows which registers are available in each mode.
Page 55: Figure 2-3 Register Organization In Arm State
Programmer’s Model FIQ mode has seven banked registers mapped to r8–r14 (r8_fiq–r14_fiq). In ARM state, many FIQ handlers do not have to save any registers. The User, IRQ, Supervisor, Abort, and undefined modes each have two banked registers mapped to r13 and r14, allowing a private SP and LR for each mode.
Page 56: Figure 2-4 Register Organization In Thumb State
Programmer’s Model 2.6.2 The Thumb-state register set The Thumb-state register set is a subset of the ARM-state set. The programmer has access to: • 8 general registers, r0–r7 • the PC • the SP • the LR • the CPSR.
Page 57: Figure 2-5 Mapping Of Thumb-State Registers Onto Arm-State Registers
Programmer’s Model 2.6.3 The relationship between ARM-state and Thumb-state registers The Thumb-state registers relate to the ARM-state registers in the following way: • Thumb-state r0–r7 and ARM-state r0–r7 are identical • Thumb-state CPSR and SPSRs and ARM-state CPSR and SPSRs are identical •...
Page 58 The CMP instruction enables you to compare high register values with low register values. The ADD instruction enables you to add high register values to low register values. For more details, see the ARM Architecture Reference Manual. 2-12 Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 59: The Program Status Registers
Programmer’s Model The program status registers The ARM7TDMI processor contains a CPSR and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts •...
Page 60 Programmer’s Model All instructions can execute conditionally in ARM state. In Thumb state, only the Branch instruction can be executed conditionally. For more information about conditional execution, see the ARM Architecture Reference Manual. 2.7.2 Control bits The bottom eight bits of a PSR are known collectively as the control bits. They are the: •...
Page 61: Table 2-2 Psr Mode Bit Values
Also, make sure that your program does not rely on reserved bits containing specific values because future processors might have these bits set to 1 or 0. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 2-15...
Page 62: Exceptions
Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example, to service an interrupt from a peripheral. Before attempting to handle an exception, the ARM7TDMI processor preserves the current processor state so that the original program can resume when the handler routine has finished.
Page 63 Forces the CPSR mode bits to a value that depends on the exception. Forces the PC to fetch the next instruction from the relevant exception vector. The ARM7TDMI processor can also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions.
Page 64 FIQ exceptions can be disabled within a privileged mode by setting the CPSR F flag. When the F flag is clear, the ARM7TDMI processor checks for a LOW level on the output of the FIQ synchronizer at the end of each instruction.
Page 65 IRQ has a lower priority than FIQ, and is masked on entry to an FIQ sequence. As with the nFIQ input, nIRQ passes into the core through a synchronizer. Irrespective of whether exception entry is from ARM state or Thumb state, an IRQ handler returns from the interrupt by executing:...
Page 66 It also means that the ARM7TDMI core always preserves r15 in an aborted LDM instruction, because r15 is always either the last register in the transfer list or not present in the transfer list.
Page 67: Undefined Instruction
When the ARM7TDMI processor encounters an instruction that neither it, nor any coprocessor in the system can handle, the ARM7TDMI core takes the undefined instruction trap. Software can use this mechanism to extend the ARM instruction set by emulating undefined coprocessor instructions.
Page 68: Table 2-5 Exception Priority Order
• When FIQs are enabled, and a Data Abort occurs at the same time as an FIQ, the ARM7TDMI processor enters the Data Abort handler, and proceeds immediately to the FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution.
Page 69: Interrupt Latencies
The minimum latency for FIQ or IRQ is the shortest time the request can take through the synchronizer, T , plus T , a total of five processor cycles. syncmin ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 2-23...
Page 70: Reset
2.10 Reset When the nRESET signal goes LOW a reset occurs, and the ARM7TDMI core abandons the executing instruction and continues to increment the address bus as if still fetching word or halfword instructions. nMREQ and SEQ indicates internal cycles during this time.
Page 71 Chapter 3 Memory Interface This chapter describes the ARM7TDMI processor memory interface. It contains the following sections: • About the memory interface on page 3-2 • Bus interface signals on page 3-3 • Bus cycle types on page 3-4 •...
Page 72: About The Memory Interface
Memory Interface About the memory interface The ARM7TDMI processor has a Von Neumann architecture, with a single 32-bit data bus carrying both instructions and data. Only load, store, and swap instructions can access data from memory. Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 73: Bus Interface Signals
Memory Interface Bus interface signals The signals in the ARM7TDMI processor bus interface can be grouped into four categories: • clocking and clock control • address class signals • memory request signals • data timed signals. The clocking and clock control signals are: •...
Page 74: Bus Cycle Types
Memory Interface Bus cycle types The ARM7TDMI processor bus interface is pipelined. This gives the maximum time for a memory cycle to decode the address and respond to the access request: • memory request signals are broadcast in the bus cycle ahead of the bus cycle to which they refer •...
Page 75: Table 3-1 Bus Cycle Types
I-cycle Internal cycle C-cycle Coprocessor register transfer cycle A memory controller for the ARM7TDMI processor must commit to a memory access only on an N-cycle or an S-cycle. 3.3.1 Nonsequential cycles A nonsequential cycle is the simplest form of bus cycle, and occurs when the processor requests a transfer to or from an address that is unrelated to the address used in the preceding cycle.
Page 76: Figure 3-2 Nonsequential Memory Cycle
This happens, for example, when an instruction is executed. If you are designing a memory controller for the ARM7TDMI core, and your memory system is unable to cope with this case, use the nWAIT signal to extend the bus cycle to allow sufficient cycles for the memory system.
Page 77: Table 3-2 Burst Types
Figure 3-3 Sequential access cycles 3.3.3 Internal cycles During an internal cycle, the ARM7TDMI processor does not require a memory access, as an internal function is being performed, and no useful prefetching can be performed at the same time. ARM DDI 0210C...
Page 78 Memory Interface Where possible the ARM7TDMI processor broadcasts the address for the next access, so that decode can start, but the memory controller must not commit to a memory access. This is shown in Figure 3-4 and, is further described in Nonsequential memory cycle on page 3-6.
Page 79: Figure 3-5 Merged Is Cycle
3.3.5 Coprocessor register transfer cycles During a coprocessor register transfer cycle, the ARM7TDMI processor uses the data buses to transfer data to or from a coprocessor. A memory cycle is not required and the memory controller does not initiate a transaction. The memory system must not drive onto the data bus during a coprocessor register transfer cycle.
Page 80: Figure 3-6 Coprocessor Register Transfer Cycles
A[31:0] nMREQ D[31:0] Memory Memory Coprocessor Figure 3-6 Coprocessor register transfer cycles 3.3.6 Summary of ARM memory cycle timing A summary of ARM7TDMI processor memory cycle timing is shown in Figure 3-7. N-cycle S-cycle I-cycle C-cycle MCLK A[31:0] nMREQ nRAS...
Page 81: Addressing Signals
All writable memory in an ARM7TDMI processor based system must support the writing of individual bytes to enable the use of the C Compiler and the ARM debug tool chain, for example Multi-ICE. ARM DDI 0210C Copyright ©...
Page 82: Table 3-3 Significant Address Bits
A writable memory system for the ARM7TDMI processor must have individual byte write enables. Both the C Compiler and the ARM debug tool chain, for example, Multi-ICE, assume that arbitrary bytes in the memory can be written. If individual byte write capability is not provided, you might not be able to use either of these tools without data corruption.
Page 83: Table 3-5 Ntrans Encoding
These instructions perform an atomic read/write operation, and can be used to implement semaphores. 3.4.7 TBIT TBIT is used to indicate the operating state of the ARM7TDMI processor. When in: • ARM state, the TBIT signal is LOW •...
Page 84: Address Timing
In most systems, particularly a DRAM-based system, it is desirable to obtain the address from ARM7TDMI processor as early as possible. When APE is HIGH then the ARM7TDMI processor address becomes valid after the rising edge of MCLK before the memory cycle to which it refers.
Page 85: Figure 3-9 Depipelined Addresses
The value of APE can be held until the memory control signals denote another nonsequential access. Previous ARM processors included the ALE signal, and this is retained for backwards compatibility. This signal also enables you to modify the address timing to achieve the same results as APE, but in a dynamic manner.
Page 86: Figure 3-10 Sram Compatible Address Timing
APE is to be used, ALE must be tied HIGH. You can obtain better system performance when the address pipeline is enabled with APE HIGH. This allows longer time for address decoding. 3-16 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 87: Data Timed Signals
3.6.1 D[31:0], DOUT[31:0], and DIN[31:0] The ARM7TDMI processor provides both unidirectional data buses, DIN[31:0], DOUT[31:0], and a bidirectional data bus, D[31:0]. The configuration input BUSEN is used to select which is active. Figure 3-11 shows the arrangement of the data buses and bus-splitter logic.
Page 88: Figure 3-12 Bidirectional Bus Timing
Figure 3-14 on page 3-19 shows how you can join the unidirectional buses up at the pads of an ASIC to connect to an external bidirectional bus. 3-18 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 89 When the ARM7TDMI processor is reading from memory DIN[31:0] is acting as an input. During write cycles the ARM7TDMI core must output data. During phase 2 of the previous cycle, the signal nRW is driven HIGH to indicate a write cycle. During the actual cycle, nENOUT is driven LOW to indicate that the processor is driving D[31:0] as an output.
Page 90: Figure 3-15 Data Write Bus Cycle
Scan Data direction nENOUT cell control from core Scan nENIN cell Write data D[31:0] from core Read data to core Figure 3-16 Data bus control circuit 3-20 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 91: Table 3-6 Tristate Control Of Processor Outputs
Table 3-6 lists the tristate control of the processor outputs. Table 3-6 Tristate control of processor outputs Processor output A[31:0] D[31:0] LOCK MAS[1:0] nOPC nTRANS ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 3-21...
Page 92 Similarly, when the bus switches back to input, the core must stop driving before the pad is enabled. Figure 3-17 on page 3-23 shows the circuit implemented in the ARM7TDMI processor test chip. 3-22 Copyright ©...
Page 93: Figure 3-17 Test Chip Data Bus Circuit
EDBE is used by the bus control logic to enable the external memory controller to arbitrate the bus and asynchronously disable the ARM7TDMI core test chip if necessary. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 3-23...
Page 94 3.6.3 Byte latch enables To ease the connection of the ARM7TDMI core to subword sized memory systems, input data and instructions can be latched on a byte-by-byte basis. You can achieve this by the use of the BL[3:0] signal as follows: •...
Page 95: Figure 3-18 Memory Access
In the second cycle, the byte for D[15:8] is latched so the halfword on D[15:0] is correctly read from memory. It does not matter that D[31:16] are unknown because the core extracts only the halfword of interest. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 3-25...
Page 96: Figure 3-19 Two-Cycle Memory Access
When connecting 8-bit to 16-bit memory systems to the processor, ensure that the data is presented to the correct byte lanes on the core as listed in Table 3-7 on page 3-27. 3-26 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 97: Table 3-7 Read Accesses
D[7:0] Note For subword reads the value is placed in the ARM register in the least significant bits regardless of the byte lane used to read the data. For example, a byte read on A[1:0] = 01 in a little-endian system means that the byte is read on bits D[15:8] but is placed in the ARM register bits [7:0].
Page 98: Figure 3-20 Data Replication
D[31:24] D[23:16] D[15:8] D[7:0] Half word write (register [15:0]) Memory interface D[31:16] D[15:0] ABCD Word write (register [31:0]) Memory interface ABCD D[31:0] Figure 3-20 Data replication 3-28 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 99: Stretching Access Times
Memory Interface Stretching access times The ARM7TDMI processor does not contain any dynamic logic that relies on regular clocking to maintain the internal state. Therefore, there is no limit upon the maximum period for which MCLK can be stretched, or nWAIT held LOW. There are two methods available to stretch access times as described in: •...
Page 100: Figure 3-21 Typical System Timing
SEQ, and the address class signals only when nWAIT is HIGH. This ensures that the state of the memory controller is not accidentally updated during an extended bus cycle. 3-30 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 101: Privileged Mode Access
10011 01100 Supervisor 10111 01000 Abort 11011 00100 Undefined 11111 00000 System Note The only time to use the nM[4:0] signals is for diagnostic and debug purposes. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 3-31...
Page 102: Reset Sequence After Power Up
They are undefined after power up. After nRESET has been taken HIGH, the ARM core does two further internal cycles before the first instruction is fetched from the reset vector (address 0x00000000 ).
Page 103 Chapter 4 Coprocessor Interface This chapter describes the ARM7TDMI core coprocessor interface. It contains the following sections: • About coprocessors on page 4-2 • Coprocessor interface signals on page 4-4 • Pipeline following signals on page 4-5 • Coprocessor interface handshaking on page 4-6 •...
Page 104: Chapter 4 Coprocessor Interface
• special processing logic, with its own data path. A coprocessor is connected to the same data bus as the ARM7TDMI processor in the system, and tracks the pipeline in the ARM7TDMI processor. This means that the coprocessor can decode the instructions in the instruction stream, and execute those that it supports.
Page 105: Table 4-1 Coprocessor Availability
4.1.1 Coprocessor availability Up to 16 coprocessors can be referenced by a system, each with a unique coprocessor ID number to identify it. The ARM7TDMI core contains one internal coprocessor: • CP14, the Debug Communications Channel (DCC) coprocessor. Other coprocessor numbers have also been reserved. Coprocessor availability is listed in Table 4-1.
Page 106: Coprocessor Interface Signals
Coprocessor Interface Coprocessor interface signals The signals used to interface the ARM7TDMI core to a coprocessor are grouped into four categories. The clock and clock control signals are: • MCLK • nWAIT • nRESET. The pipeline following signals are: •...
Page 107: Pipeline Following Signals
An instruction must be loaded into the pipeline on the falling edge of MCLK, and only when nOPC, nMREQ, and TBIT were all LOW in the previous bus cycle. These conditions indicate that this cycle is an ARM instruction fetch, so the new opcode must be read into the pipeline.
Page 108: Coprocessor Interface Handshaking
• Coprocessor data operations on page 4-10 • Coprocessor load and store operations on page 4-10. The ARM7TDMI core and any coprocessors in the system perform a handshake using the signals shown in Table 4-2. Table 4-2 Handshaking signals Signal...
Page 109: Table 4-3 Summary Of Coprocessor Signaling
The instruction has passed its conditional execution tests. If all these requirements are met, the ARM7TDMI core signals by taking nCPI LOW, this commits the coprocessor to the execution of the coprocessor instruction.
Page 110: Figure 4-1 Coprocessor Busy-Wait Sequence
Figure 4-1 Coprocessor busy-wait sequence CPA and CPB are ignored by the ARM7TDMI processor when it does not have a undefined or coprocessor instruction in the Execute stage of the pipeline. A summary of coprocessor signaling is listed in Table 4-3 on page 4-7.
Page 111: Figure 4-2 Coprocessor Register Transfer Sequence
Coprocessor register transfer instructions The coprocessor register transfer instructions, MCR and MRC, are used to transfer data between a register in the ARM7TDMI processor register bank and a register in the coprocessor register bank. An example sequence for a coprocessor register transfer is shown in Figure 4-2.
Page 112: Figure 4-3 Coprocessor Data Operation Sequence
Coprocessor data operations, CDP instructions, perform processing operations on the data held in the coprocessor register bank. No information is transferred between the ARM7TDMI processor and the coprocessor as a result of this operation. An example sequence is shown in Figure 4-3.
Page 113: Figure 4-4 Coprocessor Load Sequence
Instr fetch Instr fetch Instr fetch D[31:0] CP Data CP Data CP Data CP Data Instr fetch (LDC) (ADD) (SUB) (TST) (SUB) Figure 4-4 Coprocessor load sequence ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 4-11...
Page 114: Connecting Coprocessors
Coprocessor Interface Connecting coprocessors A coprocessor in an ARM7TDMI processor system must have 32-bit connections to: • the instruction stream from memory • data written by the core, MCR • data read by the core, MRC. The coprocessor can optionally have connections to: •...
Page 115: Figure 4-6 Coprocessor Connections With Unidirectional Bus
ANDed together, and connected to the CPA and CPB inputs on the ARM7TDMI processor. You must multiplex the output data from the coprocessors. Connecting multiple coprocessors is shown in Figure 4-7 on page 4-14. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 4-13...
Page 116: Figure 4-7 Connecting Multiple Coprocessors
Coprocessor Interface CPAn nCPI ARM core CPBn CPB2 CPA2 CPA1 CPB1 Coprocessor Coprocessor Coprocessor Figure 4-7 Connecting multiple coprocessors 4-14 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 117: If You Are Not Using An External Coprocessor
The internal coprocessor, CP14, can still be used. The coprocessor outputs from the ARM7TDMI processor are usually left unconnected but these outputs can be used in other parts of a system as follows:.
Page 118: Undefined Instructions
All coprocessors must monitor the state of the TBIT output from ARM7TDMI core. When the ARM7TDMI core is in Thumb state, coprocessors must drive CPA and CPB HIGH, and the instructions seen on the data bus must be ignored.
Page 119: Privileged Instructions
If a User mode process, with nTRANS LOW, tries to access a coprocessor instruction that can only be executed in a privileged mode, the coprocessor responds with CPA and CPB HIGH. This causes the ARM7TDMI processor to take the undefined instruction trap.
Page 121 Chapter 5 Debug Interface This chapter describes the ARM7TDMI processor debug interface. It contains the following sections: • About the debug interface on page 5-2 • Debug systems on page 5-4 • Debug interface signals on page 5-7 • ARM7TDMI core clock domains on page 5-11 •...
Page 122: Chapter 5 Debug Interface
Store Multiple ( ) can be inserted into the instruction pipeline and this exports the contents of the ARM7TDMI core registers. This data can be serially shifted out without affecting the rest of the system. In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor program running on the ARM7TDMI core.
Page 123 During normal operation, the core is clocked by MCLK and internal logic holds DCLK LOW. When the ARM7TDMI processor is in halt mode, the core is clocked by DCLK under control of the TAP state machine and MCLK can free-run. The selected clock is output on the signal ECLK for use by the external system.
Page 124: Debug Systems
5.2.1 Debug host The debug host is a computer that is running a software debugger such as the ARM Debugger for Windows (ADW). The debug host enables you to issue high-level commands such as setting breakpoints or examining the contents of memory.
Page 125: Figure 5-2 Arm7Tdmi Block Diagram
Debug Interface The ARM7TDMI processor has hardware extensions that ease debugging at the lowest level. The debug extensions: • enable you to halt program execution • examine and modify the core internal state of the core • view and modify the state of the memory system •...
Page 127: Debug Interface Signals
The following sections describe: • Entry into debug state • Action of the ARM7TDMI processor in debug state on page 5-10. 5.3.1 Entry into debug state The ARM7TDMI processor is forced into debug state following a breakpoint, watchpoint, or debug request.
Page 128: Figure 5-3 Debug State Entry
Figure 5-3 Debug state entry Entry into debug state on breakpoint The ARM7TDMI core marks instructions as being breakpointed as they enter the instruction pipeline, but the core does not enter debug state until the instruction reaches the Execute stage.
Page 129 Entry into debug state on debug request The ARM7TDMI processor can be forced into debug state on debug request in either of the following ways: •...
Page 130 Debug Interface instruction is a busy-waiting access to a coprocessor, the instruction terminates and ARM7TDMI processor enters debug state immediately. This is similar to the action of nIRQ and nFIQ. 5.3.2 Action of the ARM7TDMI processor in debug state In debug state, nMREQ and SEQ indicate internal cycles. This enables the rest of the memory system to ignore the core and function as normal.
Page 131: Arm7Tdmi Core Clock Domains
5.4.1 Clock switch during debug When the ARM7TDMI processor enters halt debug state, it switches automatically from MCLK to DCLK, it then asserts DBGACK in the HIGH phase of MCLK. The switch between the two clocks occurs on the next falling edge of MCLK. This is shown in Figure 5-4.
Page 132 5.4.2 Clock switch during test When serial test patterns are being applied to the ARM7TDMI core through the JTAG interface, the processor must be clocked using DCLK. MCLK must be held LOW. Entry into test is less automatic than debug and you must take care to prevent spurious clocking on the way into test.
Page 133: Determining The Core And System State
Before you can examine the core and system state, the debugger must determine if the processor entered debug from Thumb state or ARM state, by examining bit [4] of the EmbeddedICE-RT logic debug status register. When bit [4] is HIGH, the core has entered debug from Thumb state.
Page 134: About Embeddedice-Rt Logic
The EmbeddedICE-RT logic provides integrated on-chip debug support for the ARM7TDMI core. The EmbeddedICE-RT logic is programmed serially using the ARM7TDMI processor TAP controller. Figure 5-5 illustrates the relationship between the core, the EmbeddedICE-RT logic, and the TAP controller, showing only the pertinent signals.
Page 135 You can mask any bit so that its value does not affect the comparison. You can configure each watchpoint unit for either a watchpoint or a breakpoint. Watchpoints and breakpoints can be data-dependent in halt mode only. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 5-15...
Page 136: Disabling Embeddedice-Rt
When DBGEN is LOW: • BREAKPT and DBGRQ are ignored by the core • DBGACK is forced LOW by the ARM7TDMI core • interrupts pass through to the processor uninhibited by the debug logic • the EmbeddedICE-RT logic enters low-power mode.
Page 137: Debug Communications Channel
Debug Interface Debug Communications Channel The ARM7TDMI processor EmbeddedICE-RT logic contains a Debug Communications Channel (DCC) to pass information between the target and the host debugger. This is implemented as coprocessor 14 (CP14). The DCC comprises: • a 32-bit communications data read register •...
Page 138: Table 5-1 Dcc Register Access Instructions
You can send and receive messages through the DCC. The following sections describe: • Sending a message to the debugger on page 5-19 • Receiving a message from the debugger on page 5-19 5-18 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 139 14. When the debugger polls this register and sees that the R bit is clear, the data has been taken and the process can now be repeated. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 5-19...
Page 140 An alternative, and potentially more efficient, method to polling the debug communications control register is to use the COMMTX and COMMRX outputs from the ARM7TDMI processor. You can use these outputs to interrupt the processor when: • a word is available to be read from the DCC data read register •...
Page 141: Monitor Mode
14 (see The abort status register on page B-56). The monitor mode enable bit does not put the ARM7TDMI processor into debug state. For this reason, it is necessary to change the contents of the watchpoint registers while external memory accesses are taking place, rather than changing them when in debug state where the core is halted.
Page 143 Chapter 6 Instruction Cycle Timings This chapter describes the ARM7TDMI processor instruction cycle operations. It contains the following sections: • About the instruction cycle timing tables on page 6-3 • Branch and branch with link on page 6-4 • Thumb branch with link on page 6-5 •...
Page 144 Coprocessor register transfer, store to coprocessor on page 6-26 • Undefined instructions and coprocessor absent on page 6-27 • Unexecuted instructions on page 6-28 • Instruction speed summary on page 6-29. Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 145: About The Instruction Cycle Timing Tables
The address is incremented to prefetch instructions in most cases. Because the instruction width is four bytes in ARM state and two bytes in Thumb state, the increment varies accordingly.
Page 146: Branch And Branch With Link
The cycle timings are listed in Table 6-1 where: • pc is the address of the branch instruction • alu is the destination address calculated by the ARM7TDMI core • (alu) is the contents of that address. Table 6-1 Branch instruction cycle operations...
Page 147: Thumb Branch With Link
The first instruction acts like a simple data operation to add the PC to the upper part of the offset, storing the result in Register r14, LR. The second instruction which takes a single cycle acts in a similar fashion to the ARM state branch with link instruction. The first cycle therefore calculates the final branch destination whilst performing a prefetch from the current PC.
Page 148: Branch And Exchange
W and w represent the instruction width before and after the BX respectively. The width equals four bytes in ARM state and two bytes in Thumb state. For example, when changing from ARM to Thumb state, W equals four and w equals two •...
Page 149: Data Operations
The cycle timings are listed in Table 6-4 on page 6-8 where: • pc is the address of the branch instruction • alu is the destination address calculated by the ARM7TDMI core • (alu) is the contents of that address. ARM DDI 0210C...
Page 150: Table 6-4 Data Operation Instruction Cycles
(pc+8) dest=pc pc+12 (alu) alu+4 (alu+4) alu+8 Note The shifted register operations where the destination is the PC are not available in Thumb state. Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 151: Multiply And Multiply Accumulate
(pc+2L) pc+3L • pc+3L pc+3L pc+3L pc+3L Table 6-6 Multiply accumulate instruction cycle operations Cycle Address MAS[1:0] Data nMREQ nOPC pc+8 (pc+8) pc+8 • pc+12 pc+12 ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 152: Table 6-7 Multiply Long Instruction Cycle Operations
Table 6-8 Multiply accumulate long instruction cycle operations Cycle Address MAS[1:0] Data nMREQ nOPC pc+8 (pc+8) pc+8 • pc+12 pc+12 pc+12 pc+12 pc+12 pc+12 6-10 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 153 Instruction Cycle Timings Note The multiply accumulate, multiply long, and multiply accumulate long operations are not available in Thumb state. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 6-11...
Page 154: Load Register
Table 6-9 Load register instruction cycle operations Operation type Cycle Address MAS[1:0] Data nMREQ nOPC nTRANS normal pc+2L (pc+2L) (alu) pc+3L pc+3L dest=pc pc+8 (pc+8) pc’ pc+12 6-12 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 155: Table 6-10 Mas[1:0] Signal Encoding
Operations where the destination is the PC are not available in Thumb state. Table 6-10 MAS[1:0] signal encoding Bit [1] Bit [0] Data size byte halfword word reserved ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 6-13...
Page 156: Store Register
MAS[1:0] (see Table 6-10 on page 6-13). Table 6-11 Store register instruction cycle operations Cycle Address MAS[1:0] Data nMREQ nOPC nTRANS pc+2L (pc+2L) pc+3L 6-14 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 157: Load Multiple Registers
Table 6-12 Load multiple registers instruction cycle operations Destination registers Cycle Address MAS[1:0] Data nMREQ nOPC Single register pc+2L (pc+2L) (alu) pc+3L pc+3L Single register dest=pc pc+2L (pc+2L) pc’ pc+3L pc’ (pc’) ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 6-15...
Page 158 (alu+•) alu+• (alu+•) pc+3L pc+3L n registers (n>1) including pc pc+2L (pc+2L) (alu) • alu+• (alu+•) alu+• (alu+•) alu+• pc’ pc+3L pc’ (pc’) pc’+L (pc’+L) pc’+2L 6-16 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 159: Store Multiple Registers
Table 6-13 Store multiple registers instruction cycle operations Register Cycle Address MAS[1:0] Data nMREQ nOPC Single register pc+2L (pc+2L) pc+3L n registers (n>1) pc+8 (pc+2L) • alu+• R• alu+• R• alu+• R• pc+12 ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 6-17...
Page 160: Data Swap
Table 6-14 Data swap instruction cycle operations Cycle Address MAS [1:0] Data nMREQ nOPC LOCK pc+8 (pc+8) (Rn) pc+12 pc+12 Note The data swap operation is not available in Thumb state. 6-18 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 161: Software Interrupt And Exception Entry
Xn is the appropriate trap address. Table 6-15 Software Interrupt instruction cycle operations Cycle Address Data nMREQ nOPC nTRANS Mode [1:0] pc+2L (pc+2L) (Xn) exception Xn+4 (Xn+4) exception Xn+8 ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 6-19...
Page 162: Coprocessor Data Operation
[1:0] ready pc+8 (pc+8) pc+12 not ready pc+8 (pc+8) pc+8 • pc+8 pc+8 pc+12 Note Coprocessor data operations are not available in Thumb state. 6-20 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 163: Coprocessor Data Transfer From Memory To Coprocessor
The coprocessor is responsible for determining the number of words to be transferred, and indicates the last transfer cycle by driving CPA and CPB HIGH. The ARM7TDMI processor spends the first cycle (and any busy-wait cycles) generating the transfer address, and updates the base address during the transfer cycles.
Page 164 • pc+8 pc+8 (alu) • alu+• (alu+•) alu+• (alu+•) n+b+1 alu+• (alu+•) pc+12 Note Coprocessor data transfer operations are not available in Thumb state. 6-22 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 165: Coprocessor Data Transfer From Coprocessor To Memory
Instruction Cycle Timings 6.15 Coprocessor data transfer from coprocessor to memory The ARM7TDMI processor controls these instructions in the same way as for memory to coprocessor transfers, with the exception that the nRW line is inverted during the transfer cycle.
Page 166 [1:0] pc+8 CPdata • alu+• CPdata alu+• CPdata n+b+1 alu+• CPdata pc+12 Note Coprocessor data transfer operations are not available in Thumb state. 6-24 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 167: Coprocessor Register Transfer, Load From Coprocessor
6-21, but the transfer is limited to one word, and the ARM7TDMI core puts the data into the destination register in the third cycle. The third cycle can be merged with the next prefetch cycle into one memory N-cycle as with all processor register load instructions.
Page 168: Coprocessor Register Transfer, Store To Coprocessor
[1:0] ready pc+8 (pc+8) pc+12 pc+12 not ready pc+8 (pc+8) pc+8 • pc+8 pc+8 pc+12 pc+12 Note Coprocessor register transfer operations are not available in Thumb state. 6-26 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 169: Undefined Instructions And Coprocessor Absent
(Xn) 00100 Xn+4 (Xn+4) 00100 Xn+8 Note • Coprocessor instructions are not available in Thumb state. • CPA and CPB are HIGH during the undefined instruction trap. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 6-27...
Page 170: Unexecuted Instructions
(see Table 6-22). Table 6-22 Unexecuted instruction cycle operations Cycle Address MAS[1:0] Data nMREQ nOPC pc+2L (pc+2L) pc+3L 6-28 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 171: Instruction Speed Summary
+S + N if R15 written MSR, MRS S+N+I +S +N if R15 loaded nS+N+I +S +N if R15 loaded (n-1)S+2N S+2N+I B,BL 2S+N SWI, trap 2S+N S+mI ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 6-29...
Page 172 Instruction Cycle Timings Table 6-23 ARM instruction speed summary (continued) Instruction Cycle count Additional S+(m+1)I MULL S+(m+1)I MLAL S+(m+2)I S+bI LDC, STC (n-1)S+2N+bI N+bI+C S+(b+1)I+C 6-30 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 173: Ac And Dc Parameters
Chapter 7 AC and DC Parameters This chapter gives the AC timing parameters of the ARM7TDMI core. It contains the following sections: • Timing diagrams on page 7-2 • Notes on AC parameters on page 7-20 • DC parameters on page 7-26.
Page 175: Figure 7-1 General Timings
In Figure 7-1, nWAIT, APE, ALE, and ABE are all HIGH during the cycle shown. is the delay, on either edge (whichever is greater), from the edge of MCLK to cdel ECLK. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 176: Table 7-1 General Timing Parameters
SEQ hold time from MCLKf Minimum MCLKr to nOPC valid Maximum opcd nOPC hold time from MCLKr Minimum opch MCLKr to nRW valid Maximum nRW hold time from MCLKr Minimum Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 177: Table 7-2 Abe Address Control Timing Parameters
Address bus disable time Maximum MCLK nENOUT nenh D[31:0] dout Figure 7-3 Bidirectional data write cycle Note In Figure 7-3 DBE is HIGH and nENIN is LOW during the cycle shown. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 178: Table 7-3 Bidirectional Data Write Cycle Timing Parameters
BL[3:0] hold time from MCLKf Minimum bylh BL[3:0] set up to from MCLKr Minimum byls DIN[31:0] hold time from MCLKf Minimum DIN[31:0] setup time to MCLKf Minimum MCLKf to nENOUT valid Maximum Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 179: Table 7-5 Data Bus Control Timing Parameters
Data bus enable time from DBEr Maximum DBE to nENOUT valid Maximum dbnen Data bus disable time from DBEf Maximum DOUT[31:0] hold from MCLKf Minimum MCLKf to D[31:0] valid Maximum dout ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 180: Table 7-6 Output 3-State Time Timing Parameters
Table 7-7 Unidirectional data write cycle timing parameters Symbol Parameter Parameter type DOUT[31:0] hold time from MCLKf Minimum dohu MCLKf to DOUT[31:0] valid Maximum doutu MCLKf to nENOUT valid Maximum Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 181: Table 7-8 Unidirectional Data Read Cycle Timing Parameters
DIN[31:0] hold time from MCLKf Minimum dihu DIN[31:0] set up time to MCLKf Minimum disu MCLKf to nENOUT valid Maximum MCLK BIGEND ISYNC Figure 7-9 Configuration pin timing ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 182: Table 7-9 Configuration Pin Timing Parameters
CPA,CPB hold time from MCLKr Minimum MCLKf to nCPI valid Maximum nCPI hold time from MCLKf Minimum cpih CPA, CPB to nMREQ, SEQ Maximum cpms CPA, CPB setup to MCLKr Minimum 7-10 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 183: Table 7-11 Exception Timing Parameters
Asynchronous interrupt set up time to MCLKf for guaranteed recognition, with ISYNC=0 Minimum Reset guaranteed nonrecognition time Maximum Reset setup time to MCLKr for guaranteed recognition Minimum ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 7-11...
Page 184: Table 7-12 Synchronous Interrupt Timing Parameters
Synchronous nFIQ, nIRQ setup to MCLKf, with ISYNC=1 Minimum MCLK dbgh DBGACK dbgd BREAKPT brks brkh DBGRQ EXTERN[1] exts exth DBGRQI dbgrq RANGEOUT0 RANGEOUT1 Figure 7-13 Debug timing 7-12 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 185: Table 7-13 Debug Timing Parameters
The timing parameter used in Figure 7-14 is listed in Table 7-14. Table 7-14 DCC output timing parameters Parameter Symbol Parameter type MCLKr to COMMRX, COMMTX valid Maximum commd ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 7-13...
Page 186: Table 7-15 Breakpoint Timing Parameters
Figure 7-16 TCK and ECLK relationship Note In Figure 7-16, T is the delay, on either edge (whichever is greater), from the edge ctdel of TCK to ECLK. 7-14 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 187: Table 7-16 Tck And Eclk Timing Parameters
The timing parameters used in Figure 7-17 are listed in Table 7-17. Table 7-17 MCLK timing parameters Symbol Parameter Parameter type MCLKr to address valid Maximum addr MCLK HIGH time Minimum mckh MCLK LOW time Minimum mckl ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 7-15...
Page 188: Table 7-18 Scan General Timing Parameters
Data output hold time from TCK Minimum bsdh TDI, TMS hold from TCKr Minimum bsih TDI, TMS setup to TCKr Minimum bsis TCKf to TDO valid Maximum bsod 7-16 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 189: Table 7-19 Reset Period Timing Parameters
D[31:0], DBGACK, nCPI, nENOUT, nEXEC, nMREQ, SEQ valid Maximum rstd nRESET LOW for guaranteed reset Minimum rstl A[ ] D[ ] Figure 7-20 Output enable and disable times due to HIGHZ TAP instruction ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 7-17...
Page 190: Table 7-20 Output Enable And Disable Timing Parameters
Parameter Parameter type Output enable time Maximum Output disable time Maximum Phase 1 Phase 2 MCLK A[31:0] LOCK aleh nOPC nTRANS MAS[1:0] Figure 7-22 ALE address control 7-18 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 191: Table 7-21 Ale Address Control Timing Parameters
MCLKf to address group valid Maximum Address group output hold time from MCLKf Minimum apeh APE hold time from MCLKf Minimum APE set up time to MCLKr Minimum ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 7-19...
Page 192: Notes On Ac Parameters
Figure 7-1 on page 7-3 MAS[1:0] and LOCK hold from MCLKr Minimum Figure 7-1 on page 7-3 Hold time of BREAKPT from MCLKr Minimum Figure 7-13 on page 7-12 brkh 7-20 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 193 MCLK to ECLK delay Maximum Figure 7-1 on page 7-3 cdel TCK to boundary scan clocks Maximum clkbs MCLKr to COMMRX, COMMTX valid Maximum Figure 7-14 on page 7-13 commd ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 7-21...
Page 194 DIN[31:0] set up time to MCLKf Minimum Figure 7-8 on page 7-9 disu DOUT[31:0] hold from MCLKf Minimum Figure 7-3 on page 7-5Figure 7-5 on page 7-7 7-22 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 195 Figure 7-3 on page 7-5Figure 7-4 on page 7-6Figure 7-7 on page 7-8Figure 7-8 on page 7-9 nENOUT hold time from MCLKf Minimum Figure 7-3 on page 7-5 nenh ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 7-23...
Page 196 TCK to TCK1, TCK2 falling Maximum tckf TCK to TCK1, TCK2 rising Maximum tckr TCK to DBGACK, DBGRQI changing Maximum tdbgd TCKf to TAP outputs Maximum tpfd 7-24 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 197 TCKr Maximum trsts nWAIT hold from MCLKf Minimum Figure 7-17 on page 7-15 nWAIT setup to MCLKr Minimum Figure 7-17 on page 7-15 ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 7-25...
Page 198: Dc Parameters
AC and DC Parameters DC parameters Contact your supplier for information on: • operating conditions • maximum ratings. 7-26 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 199 Appendix A Signal and Transistor Descriptions This appendix describes the signals and transistors in the ARM7TDMI processor. It contains the following sections: • Transistor dimensions on page A-2 • Signal types on page A-3 • Transistor dimensions on page A-2.
Page 200: Appendix A Signal And Transistor Descriptions
Signal and Transistor Descriptions Transistor dimensions Table A-1 shows the dimensions of the output driver for a 0.18µm ARM7TDMI r4p1 processor. Table A-1 Transistor gate dimensions of the output driver for a 0.18µm process MOSFET Width Length type 16.2µm 0.18µm 8.28µm...
Page 201: Signal Types
Signal and Transistor Descriptions Signal types Table A-2 lists the signal types used in the ARM7TDMI r4p1 processor. Table A-2 Signal types Type Description Input CMOS thresholds Power Output ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 202: Signal Descriptions
Signal and Transistor Descriptions Signal descriptions Table A-3 describes all the signals used for the ARM7TDMI r4p1 processor. Table A-3 Signal descriptions Name Type Description A[31:0] This is the 32-bit address bus. ALE, ABE, and APE are used to control when the address bus is valid.
Page 203 Placed LOW by the coprocessor when it is ready to start the operation requested by the processor. Coprocessor busy It is sampled by the processor when MCLK goes HIGH in each cycle in which nCPI is LOW. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 204 Debug enable This signal must be HIGH to enable the EmbeddedICE-RT logic to function. DBGRQ This is a level-sensitive input, that when HIGH causes ARM7TDMI core to enter debug state after executing the current instruction. This enables Debug request external hardware to force the ARM7TDMI core into debug state, in addition to the debugging features provided by the EmbeddedICE-RT logic.
Page 205 Boundary scan cell enable This must be left unconnected, if an external boundary-scan chain is not connected. ECAPCLK Only used on the ARM7TDMI test chip, and must otherwise be left unconnected. EXTEST capture clock ECAPCLKBS Used to capture the device inputs of an external boundary-scan chain during EXTEST.
Page 206 This must be LOW for the data bus to be driven during write cycles. NOT enable input Can be used in conjunction with nENOUT to control the data bus during write cycles. See Chapter 3 Memory Interface. Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 207 See Chapter 3 Memory Interface. nENOUTI During a coprocessor register transfer C-cycle from the EmbeddedICE-RT communications channel coprocessor to the ARM core, this signal goes Not enable output LOW. This can be used to aid arbitration in shared bus systems.
Page 208 HIGH. EmbeddedICE-RT RANGEOUT0 This signal is independent of the state of the watchpoint enable control bit. RANGEOUT0 changes when ECLK is LOW. A-10 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 209 HIGH. Sequential address In ARM state the new address can be for the same word or the next. In THUMB state, the same halfword or the next. It can be used, in combination with the low-order address lines, to indicate that the next cycle can use a fast memory mode (for example DRAM page mode) or to bypass the address translation system.
Page 210 Under normal operating conditions TBE must be HIGH. TBIT When the processor is executing the THUMB instruction set, this is HIGH. It is LOW when executing the ARM instruction set. This signal changes in phase two in the first execute cycle of a BX instruction.
Page 211: Appendix B Debug In Depth
Appendix B Debug in Depth This appendix describes the debug features of the ARM7TDMI core in further detail and includes additional information about the EmbeddedICE-RT logic. It contains the following sections: • Scan chains and the JTAG interface on page B-3 •...
Page 212 • The abort status register on page B-56 • Coupling breakpoints and watchpoints on page B-57 • EmbeddedICE-RT timing on page B-59 • Programming restriction on page B-60. Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 213: Scan Chains And The Jtag Interface
The control signals provided for this scan chain are described in Scan chain 3 on page B-20. Two additional scan chains exist (numbered four and eight), but these are reserved for ARM use only.
Page 214: Figure B-1 Arm7Tdmi Core Scan Chain Arrangements
Figure B-1 ARM7TDMI core scan chain arrangements Scan chain 0 Scan chain 0 enables access to the entire periphery of the ARM7TDMI core, including the data bus. The scan chain functions enable inter-device testing (EXTEST) and serial testing of the core (INTEST). The order of the scan chain, from search data in to out, is: Data bus bits 0 to 31.
Page 215: Figure B-2 Test Access Port Controller State Transitions
Exit2-IR tms=1 tms=1 Update-DR Update-IR tms=0 tms=1 tms=1 tms=0 Figure B-2 Test access port controller state transitions From IEEE Std 1149.1-1990. Copyright 1999 IEEE. All rights reserved. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 216: Resetting The Tap Controller
You must use nTRST to reset the boundary-scan interface at least once after power up. After this the TAP controller state machine can be put into the TEST-LOGIC RESET state to subsequently reset the boundary-scan interface. Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 217: Pullup Resistors
To minimize static current draw, these resistors are not fitted to the ARM7TDMI core. Accordingly, the four inputs to the test interface, the nTRST, TDI, and TMS signal plus TCK, must all be driven to good logic levels to achieve normal circuit operation.
Page 218: Instruction Register
The fixed value b0001 is loaded into the instruction register during the CAPTURE-IR controller state. The least significant bit of the instruction register is scanned in and scanned out first. Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 219: Public Instructions
• IDCODE (b1110) on page B-12 • BYPASS (b1111) on page B-12. B.5.1 EXTEST (b0000) The selected scan chain is placed in test mode by the EXTEST instruction. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 220 B.5.3 SAMPLE/PRELOAD (b0011) This instruction is included for production test only and must never be used on the scan chains provided by the ARM7TDMI core. It can be used on user-added scan chains such as boundary-scan chains. B.5.4 RESTART (b0100) The RESTART instruction restarts the processor on exit from debug state.
Page 221 TDO after a delay of one TCK cycle. The first bit shifted out is a 0. • In the UPDATE-DR state, the bypass register is not affected. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-11...
Page 222 TDI and TDO. The register is a 32-bit register that enables the manufacturer, part number, and version of a component to be read through the TAP. See ARM7TDMI core device IDentification (ID) code register on page B-14 for details of the ID register format.
Page 223 BYPASS does not enable the processor to exit debug state or synchronize to MCLK for a system-speed access while in debug state. You must use RESTART to achieve this. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-13...
Page 224: Test Data Registers
1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 Version Part number Manufacturer identity Figure B-3 ID code register format B-14 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 225 SCAN_N instruction is executed, or when a reset occurs. On reset, scan chain 0 is selected as the active scan chain. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-15...
Page 226: Table B-2 Scan Chain Number Allocation
The TAP controller can be used to drive external scan chains in addition to those within the ARM7TDMI macrocell. The external scan chain must be assigned a number and control signals for it can be derived from SCREG[3:0], IR[3:0], TAPSM[3:0], TCK1, and TCK2.
Page 227: Figure B-4 Output Scan Cell
All the control signals for the scan cells are generated internally by the TAP controller. The action of the TAP controller is determined by the current instruction and the state of the TAP state machine. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-17...
Page 228 During RUN-TEST-IDLE, the core is clocked. Usually, the TAP controller only spends one cycle in RUN-TEST-IDLE. The whole operation can then be repeated. For a description of the core clocks during test and debug, see The ARM7TDMI core clocks on page B-22.
Page 229 See System speed access on page B-32 for further details. After the ARM7TDMI core has entered debug state, the first time this bit is captured and scanned out, its value tells the debugger if the core entered debug state because of a breakpoint (bit [33] clear) or a watchpoint (bit [33] set).
Page 230 User defined. Scan chain 3 control signals are provided so that an optional external boundary-scan chain can be controlled through the ARM7TDMI core. Typically, this is used for a scan chain around the pad ring of a packaged device. The following control signals are provided which are generated only when scan chain 3 has been selected.
Page 231 When an external scan chain is in use, SDOUTBS must be connected to the serial data output of the external scan chain and SDINBS must be connected to the serial data input of the scan chain. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-21...
Page 232: The Arm7Tdmi Core Clocks
During normal operation, the core is clocked by MCLK and internal logic holds DCLK LOW. When the ARM7TDMI core is in debug state, the core is clocked by DCLK under control of the TAP state machine and MCLK can free-run. The selected clock is output on the signal ECLK for use by the external system.
Page 233 On the way into test, MCLK must be held LOW. The TAP controller can now be used to serially test the ARM7TDMI core. If scan chain 0 and INTEST are selected, DCLK is generated while the state machine is in the RUN-TEST-IDLE state. During EXTEST, DCLK is not generated.
Page 234: Determining The Core And System State In Debug State
When the processor has entered debug state from Thumb state, the simplest course of action is for the debugger to force the core back into ARM state. The debugger can then repeat the same sequence of instructions to determine the processor state.
Page 235 Executing instructions this slowly is acceptable for accessing the core state because the ARM7TDMI core is fully static. However, you cannot use this method for determining the state of the rest of the system.
Page 236 LOW, after it has synchronized back to system speed. This transition is used by the memory controller to arbitrate if the ARM7TDMI core can have the bus in the next cycle. If the bus is not available, the core can have its clock stalled indefinitely. The only way to tell that the memory access has completed is to examine the state of both nMREQ and DBGACK.
Page 237 The ARM7TDMI core synchronizes back to MCLK. Bit [33] of scan chain 1 is used to force the ARM7TDMI core to resynchronize back to MCLK, as follows: The penultimate instruction of the debug sequence is scanned in with bit [33] set HIGH.
Page 238: Figure B-6 Debug Exit Sequence
Figure B-6 shows that the first memory access that has not been counted before occurs in the cycle after DBGACK goes LOW, so this is when the counter must be re-enabled. B-28 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 240: Behavior Of The Program Counter In Debug State
The debugger must keep track of what happens to the program counter, so that the ARM7TDMI core can be forced to branch back to the place at which program flow was interrupted by debug. Program flow can be interrupted by any of the following: •...
Page 241 A similar sequence follows when an interrupt, or any other exception, occurs during a watchpointed memory access. The ARM7TDMI core enters debug state in the mode of the exception. The debugger must check to see if an exception has occurred by examining the current and previous mode, in the CPSR and SPSR, and the value of the PC.
Page 242 System speed instructions access the memory system and so it is possible for aborts to take place. If an abort occurs during a system-speed memory access, the ARM7TDMI core enters abort mode before returning to debug state.
Page 243: Priorities And Exceptions
If an interrupt is pending during the instruction prior to entering debug state, the ARM7TDMI core enters debug state in the mode of the interrupt. On entry to debug state, the debugger cannot assume that the ARM7TDMI core is in the mode expected by the user program.
Page 244 Debug in Depth B.10.3 Data Aborts When a Data Abort occurs on a watchpointed access, the ARM7TDMI core enters debug state in abort mode. The watchpoint, therefore, has higher priority than the abort, but the ARM7TDMI core remembers that the abort happened.
Page 245: Scan Chain Cell Data
Scan chain 0 cells • Scan chain 1 cells on page B-40. B.11.1 Scan chain 0 cells The ARM7TDMI core provides data for scan chain 0 cells as listed in Table B-3. Table B-3 Scan chain 0 cells Number Signal...
Page 246 Input/output D[30] Input/output D[31] Input/output nENIN Input nENOUT Output LOCK Output BIGEND Input Input MAS[0] Output MAS[1] Output BL[0] Input BL[1] Input BL[2] Input BL[3] Input Output B-36 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 247 Output nM[3] Output nM[2] Output nM[1] Output nM[0] Output nEXEC Output INSTRVALID Output Input Input Input TBIT Output nWAIT Input A[31] Output A[30] Output A[29] Output ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-37...
Page 248 Output A[16] Output A[15] Output A[14] Output A[13] Output A[12] Output A[11] Output A[10] Output A[9] Output A[8] Output A[7] Output A[6] Output A[5] Output A[4] Output B-38 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 249 Input DBGEN Input Input Input BUSEN Input EXTERN0 Input EXTERN1 Input BREAKPT Input DBGACK Output RANGEOUT0 Output RANGEOUT1 Output nENOUT1 Output COMMTX Output COMMRX Output DBGRQI Output ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-39...
Page 250: Table B-4 Scan Chain 1 Cells
Debug in Depth B.11.2 Scan chain 1 cells The ARM7TDMI core provides data for scan chain 1 cells as listed in Table B-4. Table B-4 Scan chain 1 cells Number Signal Type D[0] Input/output D[1] Input/output D[2] Input/output D[3] Input/output...
Page 251 Table B-4 Scan chain 1 cells (continued) Number Signal Type D[23] Input/output D[24] Input/output D[25] Input/output D[26] Input/output D[27] Input/output D[28] Input/output D[29] Input/output D[30] Input/output D[31] Input/output BREAKPT Input ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-41...
Page 252: The Watchpoint Registers
Watchpoint 1 address value 10001 Watchpoint 1 address mask 10010 Watchpoint 1 data value 10011 Watchpoint 1 data mask 10100 Watchpoint 1 control value 10101 Watchpoint 1 control mask B-42 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 253: Figure B-7 Embeddedice-Rt Block Diagram
The data to be written is shifted into the 32-bit data field. The address of the register is shifted into the 5-bit address field. The read/write bit is set. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-43...
Page 254 B.12.3 The control registers The control value and control mask registers are mapped identically in the lower eight bits, as shown in Figure B-8 on page B-45. B-44 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 255: Table B-6 Mas[1:0] Signal Encoding
Can be referred to the chain output of another watchpoint to implement, for example, debugger requests of the form: . In the breakpoint on address YYY only when in process XXX ARM7TDMI core EmbeddedICE-RT logic, the CHAINOUT ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-45...
Page 256 For each of the bits [7:0] in the control value register, there is a corresponding bit in the control mask register. These bits remove the dependency on particular signals. B-46 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 257: Programming Breakpoints
Program its address value register with the address of the instruction to be breakpointed. For an ARM-state breakpoint, program bits [1:0] of the address mask register to b11. For a breakpoint in Thumb state, program bits [1:0] of the address mask register to b01.
Page 258 To set the software breakpoint: Read the instruction at the desired address and store it away. Write the special bit pattern representing a software breakpoint at the address. B-48 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 260: Programming Watchpoints
Many other ways of programming the registers are possible. For instance, you can provide simple range breakpoints by setting one or more of the address mask bits. B-50 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 261: The Debug Control Register
Table B-8 on page B-52. • If clear, interrupts are enabled. Used to force the value on DBGRQ. Used to force the value on DBGACK. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-51...
Page 262: Table B-8 Interrupt Signal Control
When the condition is set up in all the processors, it can be applied to them simultaneously by entering the RUN-TEST-IDLE state. B-52 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 263 [0] of the debug control register to generate the external value of DBGACK seen at the periphery of the ARM7TDMI core. This enables the debug system to signal to the rest of the system that the core is still being debugged even when system-speed accesses are being performed (when the internal DBGACK signal from the core is LOW).
Page 264: The Debug Status Register
Enable the value on the synchronized version of DBGACK to be read. The structure of the debug control and status registers is shown in Figure B-11 on page B-55. B-54 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 265: Figure B-11 Debug Control And Status Register Structure
Synch DBGRQ (from ARM7TDMI input) Bit 0 DBGACK DBGACK (to ARM7TDMI output) Bit 0 DBGACKI Synch DBGACK (from core) Figure B-11 Debug control and status register structure ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-55...
Page 266: The Abort Status Register
DbgAbt Figure B-12 Debug abort status register This bit is set when the ARM7TDMI core takes a prefetch or data abort as a result of a breakpoint or watchpoint. If, on a particular instruction or data fetch, both the debug abort and the external abort signal are asserted, then the external abort takes priority, and the DbgAbt bit is not set.
Page 267: Coupling Breakpoints And Watchpoints
Cv[8:0] be the value in the control value register be the value in the control mask register Cm[7:0] be the combined control bus from the ARM7TDMI core, other C[9:0] watchpoint registers and the EXTERN signal. CHAINOUT signal The CHAINOUT signal is derived as follows:...
Page 268 Program all other Watchpoint 0 as normal for a breakpoint. If Watchpoint 0 matches but Watchpoint 1 does not, that is the RANGE input to Watchpoint 0 is 0, the breakpoint is triggered. B-58 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 269: Embeddedice-Rt Timing
ECLK. Sufficient set-up and hold time must therefore be enabled for these signals. See Chapter 7 AC and DC Parameters for details of the required setup and hold times for these signals. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-59...
Page 270: Programming Restriction
B.20 Programming restriction Because the monitor mode enable bit does not put the ARM7TDMI into debug state, it is necessary to change the contents of the watchpoint registers while external memory accesses are taking place, rather changing them when in debug state (where the core is halted).
Page 271: Appendix C
Appendix C Differences Between Rev 3a and Rev 4 This appendix describes the differences between Rev 3a and Rev 4 of the ARM7TDMI processor. It contains the following sections: • Summary of differences between Rev 3a and Rev 4 on page C-2 •...
Page 272: Appendix C Differences Between Rev 3A And Rev
Differences Between Rev 3a and Rev 4 Summary of differences between Rev 3a and Rev 4 The changes incorporated in ARM7TDMI Rev 4 are as follows: • improved low voltage operation • addition of EmbeddedICE-RT logic • enhancement to ETM interface •...
Page 273: Detailed Descriptions Of Differences Between Rev 3A And Rev 4
EmbeddedICE-RT is an enhanced implementation of the EmbeddedICE logic that was part of the ARM7TDMI Rev 3a. The extra feature provided by EmbeddedICE-RT is that upon a breakpoint or watchpoint, the core can be forced to take an exception, rather than simply entering debug state.
Page 274 To improve performance, only one access is required to read both the data and the status bit, in the ARM7TDMI Rev 4 because the status bit is now included in the LSB of the address field which is read from the scan chain.
Page 275 ARM7TDMI Rev 3a. C.2.9 Increased power consumption It is estimated that the ARM7TDMI Rev 4 will consume 10% less power than the ARM7TDMI Rev 3a on the same process. ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved.
Page 277: Glossary
A procedure shared by many different instructions, for generating values used by the Addressing modes instructions. For four of the ARM addressing modes, the values generated are memory addresses (which is the traditional role of an addressing mode). A fifth addressing mode generates values to be used as operands by data-processing instructions.
Page 278 An abort that is generated by the external memory system. External abort Fast interrupt. See In-circuit emulator. A mathematical quantity that when applied to itself under a given binary operation Idempotent equals itself. Glossary-2 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 279 See Link register A complex logic block with a defined interface and behavior. A typical VLSI system Macrocell will comprise several macrocells (such as an ARM7TDMI, an ETM7, and a memory block) plus application-specific logic. Memory Management Unit Allows control of a memory system. Most of the control is provided through translation tables held in memory.
Page 280 Should be written as zero (or all 0s for bit fields) by software. Values other than zero produce unpredictable results. See also Should Be One fields. Software Interrupt Instruction This instruction (SWI) enters Supervisor mode to request a particular operating system function. Glossary-4 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 281 JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is nTRST. A halfword which specifies an operation for an ARM processor in Thumb state to Thumb instruction perform. Thumb instructions must be halfword-aligned.
Page 283 7-16 fields 1-19 coprocessor register transfer 3-9 synchronous interrupt 7-12 operand 2 1-18 internal 3-7 TCK and ECLK realtionship 7-14 register organization 2-9 merged I-S 3-8 ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. Index-1...
Page 284 1 B-19 signaling 4-7 determining core state 5-13, B-24 scan chain 1 cells B-40 timing 7-10 determining system state 5-13, B-26 scan chain 2 B-19 Index-2 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...
Page 285: Figure 3-4 Internal Cycles
Instruction register B-8 entering 2-17 Instruction set FIQ 2-18 ARM 1-5 Operating modes 2-7 IRQ 2-19 ARM formats 1-12 Operating states 2-3 leaving 2-18 summary 1-11 switching states 2-3 ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. Index-3...
Page 286 B-40 Scan chain 2 B-5, B-19 Scan chain 3 B-20 Scan chains Undefined instruction trap 1-12 implementation B-3 undefined instructions 6-27 JTAG interface B-3 Undefined Mode 2-7 Index-4 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C...

ARM ARM7TDMI Technical Reference Manual

Preface

Chapter 1 Introduction

Chapter 2 Programmer's Model

Chapter 3 Memory Interface

Chapter 4 Coprocessor Interface

Chapter 5 Debug Interface

Chapter 6 Instruction Cycle Timings

Chapter 7 Ac and DC Parameters

Appendix A Signal and Transistor Descriptions

Appendix B Debug in Depth

Appendix C

Appendix C Differences between Rev 3A and Rev

Glossary

Quick Links

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Summary of Contents for ARM ARM7TDMI