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ARM DDI 0301H
ID012310
•
accessible in both User and Privileged modes.
Table 3-79 lists the results of attempted access for each mode.
Table 3-79 Results of access to the Data Synchronization Barrier operation
To use the Data Memory Barrier operation write CP15 with <Rd> SBZ and:
•
Opcode_1 set to 0
•
CRn set to c7
•
CRm set to c10
•
Opcode_2 set to 4.
For example:
MCR p15,0,<Rd>,c7,c10,4
For more details, see Explicit Memory Barriers on page 6-25.
Note
The W bit that usually enables the Write Buffer is not implemented in ARM1176JZF-S
processors, see c1, Control Register on page 3-44.
This instruction acts as an explicit memory barrier. This instruction completes when all explicit
memory transactions occurring in program order before this instruction are completed. No
instructions occurring in program order after this instruction are executed until this instruction
completes. Therefore, no explicit memory transactions occurring in program order after this
instruction are started until this instruction completes. See Explicit Memory Barriers on
page 6-25.
It can be used instead of Strongly Ordered memory when the timing of specific stores to the
memory system has to be controlled. For example, when a store to an interrupt acknowledge
location must be completed before interrupts are enabled.
The Data Synchronization Barrier operation can be performed in both privileged and User
modes of operation.
Data Memory Barrier operation
The purpose of the Data Memory Barrier operation is to ensure that all outstanding explicit
memory transactions complete before any following explicit memory transactions begin. This
ensures that data in memory is up to date before any memory transaction that depends on it.
The Data Memory Barrier operation is:
•
in CP15 c7
•
a 32-bit write only operation, common to the Secure and Non-secure worlds
•
accessible in User and Privileged mode.
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; Data Synchronization Barrier operation.
System Control Coprocessor
Read
Write
Undefined exception
Data
3-84
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