ARM ARM1176JZF-S Technical Reference Manual page 147

CRn Op1
c2 0
c3 0
c4
c5 0
c6 0
c7 0
ARM DDI 0301H
ID012310
CRm Op2 Register or operation
c0 0 Translation Table Base 0
1 Translation Table Base 1
2 Translation Table Base Control
c0 0 Domain Access Control
Not used
c0 0 Data Fault Status
1 Instruction Fault Status
c0 0 Fault Address
1 Watchpoint Fault Address
2 Instruction Fault Address
c0 4 Wait For Interrupt
c4 0 PA
c5 0 Invalidate Entire Instruction
Cache
1 Invalidate Instruction Cache
Line by MVA
2 Invalidate Instruction Cache
Line by Index
4 Flush Prefetch Buffer
6 Flush Entire Branch Target
Cache
7 Flush Branch Target Cache
Entry by MVA
c6 0 Invalidate Entire Data Cache
1 Invalidate Data Cache Line by
MVA
2 Invalidate Data Cache Line by
Index
c7 0 Invalidate Both Caches
c8 0-3 VA to PA translation in the
current world
4-7 VA to PA translation in the
other world
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Table 3-2 Summary of CP15 registers and operations (continued)
S type
R/W, B, X
R/W, B
R/W, B, X
R/W, B, X
R/W, B
R/W, B
R/W, B
R/W
R/W, B
WO
R/W, B
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
System Control Coprocessor
NS Reset
Page
type value
R/W page 3-57
0x00000000
R/W page 3-59
0x00000000
R/W page 3-60
0x00000000
R/W page 3-63
0x00000000
R/W page 3-64
0x00000000
R/W 0x00000000 page 3-66
R/W 0x00000000 page 3-68
NA 0x00000000 page 3-69
R/W 0x00000000 page 3-69
WO - page 3-85
R/W page 3-80
0x00000000
WO, X - page 3-71
WO - page 3-71
WO - page 3-71
WO
- page 3-79
WO - page 3-79
WO - page 3-79
NA - page 3-71
WO - page 3-71
WO - page 3-71
NA - page 3-71
WO - page 3-82
NA - page 3-83
3-15