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3.2.58
c15, Instruction Cache Master Valid Register
ARM DDI 0301H
ID012310
You can use the System Validation Cache Size Mask Register, in a validation simulation
environment, to perform validation with cache and TCM sizes that appear to be a different size
from those that are actually implemented. The validation environment for the processor contains
validation RAMs that support cache and TCM size masking using this register. When you write
to the System Validation Cache Size Mask Register, the processor behaves as though the caches
and TCMs are the sizes that are written to the register. The sizes written to the register are
reflected in:
•
The sizes of the cache and TCM RAMs.
•
The sizes of the caches in the Cache Type Register, see c0, Cache Type Register on
page 3-21, the number of Instruction and Data TCM banks in the TCM Status Register,
see c0, TCM Status Register on page 3-24, the sizes of the TCMs in the Instruction TCM
Region Register, see c9, Instruction TCM Region Register on page 3-91, and the Data
TCM Region Register, see c9, Data TCM Region Register on page 3-89.
•
The number and use of cache master valid bits, see Cache Master Valid Registers on
page 3-8.
•
The hazard detection logic that prevents the same line being allocated twice into the
caches.
•
The DMA. If the TCMs are both masked as not present, then the DMA also appears not
to be present.
Note
You must not modify the System Validation Cache Size Mask Register in a manufactured
device. Physical RAMs do not support cache and TCM size masking. Therefore, any attempt to
mask cache and TCM sizes using this register causes address aliasing effects and problems with
cache master valid bits, that result in incorrect operation and Unpredictable effects.
The purpose of the Instruction Cache Master Valid Register is to save and restore the instruction
cache master valid bits on entry to and exit from dormant mode, see Dormant mode on
page 10-4. You might also use this register during debug.
The Instruction Cache Master Valid Register is:
•
in CP15 c15
•
a 32-bit read/write register in Secure world only
•
accessible in privileged modes only.
The number of Master Valid bits in the register is a function of the cache size. There is one
Master Valid bit for each 8 cache lines:
For instance, there are 64 Master Valid bits for a 16KB cache. You can access Master Valid bits
through 32-bit registers indexed using Opcode_2. The maximum number of 32-bit registers
required for the largest cache size, 64KB, is 8. The Master Valid bits fill the registers from the
LSB of the lowest numbered register upwards.
Writes to unimplemented Valid bits have no effect, and reads return 0. The reset value is 0.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
System Control Coprocessor
cache size
Master Valid bits =
line length in bytes x 8
3-147
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