Table 21-7 Fldm-Fadds Raw Hazard; Table 21-8 Fldm-Short Vector Fadds Raw Hazard - ARM ARM1176JZF-S Technical Reference Manual

Instruction
FLDM
FADDS
21.7.3 Load multiple-short vector CDP RAW hazard example
Instruction
FLDM
FADDS
21.7.4 CDP-CDP RAW hazard example
ARM DDI 0301H
ID012310
Table 21-7 lists the VFP11 pipeline stages for Example 21-5 on page 21-13.
Instruction cycle number
1 2 3 4
D I E M1
- D I I
In Example 21-6, the short vector FADDS is stalled in the Issue stage until the FLDM loads all
source registers required by the FADDS. In this case, the FADDS is stalled for three cycles.
Because the FADDS depends on the FLDM for only one register, S7, it does not have to wait
for completion of the FLDM. The S7 data is forwarded in cycle 6. The LEN field contains b011,
selecting a vector length of four iterations. The STRIDE field contains b00, selecting a vector
stride of one. The first source vector uses registers S7, S0, S1, and S2, and the only FADDS
source register loaded by the FLDM is S7. This example is based on the assumption that the
remaining source and destination registers are available to the FADDS in cycle 6.
FLDM [R2], {S7-S14}
FADDS S16, S7, S25
Table 21-8 lists the VFP11 pipeline stages of the FLDM and the first iteration of the short vector
FADDS for Example 21-6.
Instruction cycle number
1 2 3 4 5
D I E M1 M2
- D I I I
In Example 21-7, the FADDS is stalled in the Issue stage for seven cycles until the FMULS data
is written and forwarded in cycle 10 to the Issue stage of the FADDS.
FMULS S4, S1, S0
FADDS S5, S4, S3
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Table 21-7 FLDM-FADDS RAW hazard

5 6 7 8 9
M2 W W W W
I I I I I
Example 21-6 FLDM-short vector FADDS RAW hazard

Table 21-8 FLDM-short vector FADDS RAW hazard

6 7 8 9 10
W W W W -
I E1 E1 E1 E1
Example 21-7 FMULS-FADDS RAW hazard
VFP Instruction Execution
10 11 12 13 14
- - - - -
E1 E2 E3 E4 E5
11 12 13 14 15
- - - - -
E2 E3 E4 E5 E6
15 16
- -
E6 E7
16 17
- -
E7 W
21-14