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7.2.2
Cache functional description
7.2.3
Cache control operations
ARM DDI 0301H
ID012310
•
The cache can be disabled independently from the TCM, under control of the appropriate
bits in CP15 c1. The cache can be disabled in Secure state while enabled in Non-secure
state and enabled in Secure state while disabled in Non-secure state.
The CL bit in the system control coprocessor, see c1, Non-Secure Access Control Register
on page 3-55, reserves cache lockdown registers for Secure world operation. When the CL
bit is 0 the cache lockdown registers are only available in the Secure world. When the CL
bit is 1 they are available for both Secure and Non-secure operation.
•
Data cache misses are nonblocking with three outstanding Data Cache misses being
supported.
•
Streaming of sequential data from LDM and LDRD operations, and for sequential
instruction fetches is supported.
The cache and TCM exist to perform associative reads and writes on requested addresses. The
steps involved in this for reads are as follows:
1.
The lower bits of the virtual address are used as the virtual index for the Tag and RAM
blocks, including the TCM.
2.
In parallel the MicroTLB is accessed to perform the virtual to physical address translation.
3.
The physical addresses read from the Tag RAMs and the TCM base address register, and
the Write Buffer address registers, in parallel with the NS Tag, are compared with the
physical address from the MicroTLB. The processor also compares the NS Tag, that the
processor stores in the Tag RAMs along with the physical address, with the NS attribute
from the MicroTLB. Both comparisons form hit signals for each of the cache ways.
4.
The hit signals are used to select the data from the cache way that has a hit. Any bytes
contained in both the data RAMs and the Write Buffer entries are taken from the Write
Buffer. If two or three Write Buffer entries are to the same bytes, the most recently written
bytes are taken.
The steps for writes are as follows:
1.
The lower bits of the virtual address are used as the virtual index for the Tag blocks.
2.
In parallel, the MicroTLB is accessed to perform the virtual to physical address
translation.
3.
The physical addresses read from the Tag RAMs and the TCM base address register are
compared with the physical address from the MicroTLB. The processor also compares the
NS Tag, that it stores in the Tag RAMs along with the physical address, with the NS
attribute from the MicroTLB. Both comparisons form hit signals for each of the cache
ways.
4.
If a cache way, or the TCM, has recorded a hit, then the write data is written to an entry
in the Cache Write Buffer, along with the cache way, or TCM, that it must take place to.
5.
The contents of the Cache Write Buffer are held until a subsequent write or CP15
operation requires space in the Write Buffer. At this point the oldest entry in the Cache
Write Buffer is written into the cache.
c7, Cache operations on page 3-69 describes the cache control operations that are supported by
the processor. The processor supports all the block cache control operations in hardware.
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Level One Memory System
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