Table 20-9 Media And Vfp Feature Register 0 Bit Functions; Figure 20-8 Media And Vfp Feature Register 0 Format - ARM ARM1176JZF-S Technical Reference Manual

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20.4.5
Media and VFP Feature Register 0
Bits
Name
[31:28]
-
[27:24]
-
[23:20]
-
[19:16]
-
[15:12]
-
[11:8]
-
[7:4]
-
[3:0]
-
ARM DDI 0301H
ID012310
The purpose of the Media and VFP Feature Register 0 is to provide information about the
features that the VFP unit contains.
Media and VFP Feature Register 0 is:
a 32-bit read-only register
accessible in any mode when the VFP is enabled by the EN bit, see Floating-point
exception register, FPEXC on page 20-16
accessible only in Privileged modes when the VFP is disabled by the EN bit.
Figure 20-8 shows the bit arrangement for Media and VFP Feature Register 0.
31
-
-
Table 20-9 shows how the bit values correspond with the Media and VFP Feature Register 0
functions.
Function
Indicates the VFP hardware support level when user traps are disabled.
, In ARM1176JZF-S processors when Flush-to-Zero and Default_NaN and Round-to-Nearest are
0x1
all selected in FPSCR, the coprocessor does not require support code. Otherwise floating point
support code is required.
Indicates support for short vectors.
0x1
, ARM1176JZF-S processors support short vectors.
Indicates support for hardware square root.
, ARM1176JZF-S processors support hardware square root.
0x1
Indicates support for hardware divide.
, ARM1176JZF-S processors support hardware divide.
0x1
Indicates support for user traps.
0x1
, ARM1176JZF-S processors support software traps, support code is required.
Indicates support for double precision VFP.
, ARM1176JZF-S processors support v2.
0x1
Indicates support for single precision VFP.
0x1
, ARM1176JZF-S processors support v2.
Indicates support for the media register bank.
, ARM1176JZF-S processors support 16, 64-bit registers.
0x1
The values in the Media and VFP Feature Register 0 are implementation defined.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
16 15
-
-
-

Figure 20-8 Media and VFP Feature Register 0 format

Table 20-9 Media and VFP Feature Register 0 bit functions

VFP Programmer's Model
8 7
3
-
-
-
20-19
0

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