Figure 4-5 Load Unsigned Halfword, Big-Endian; Figure 4-6 Load Signed Halfword, Little-Endian - ARM ARM1176JZF-S Technical Reference Manual

4.3.6 Load signed halfword, little-endian
4.3.7 Load signed halfword, big-endian
ARM DDI 0301H
ID012310
If strict alignment fault checking is enabled and Address bit 0 is not zero, then a Data Abort is
generated and the MMU returns a Misaligned fault in the Fault Status Register.
The addressed byte-pair is loaded from memory into the low 16-bits of the general-purpose
register, so that the least-significant addressed byte in memory appears in bits [7:0] of the ARM
register and the upper 16 bits are sign-extended from bit 15, as Figure 4-6 shows.
In Figure 4-6, se1 means bit 15, b1 bit [7], sign extended.
If strict alignment fault checking is enabled and Address bit 0 is not zero, then a Data Abort is
generated and the MMU returns a Misaligned fault in the Fault Status Register.
The addressed byte-pair is loaded from memory into the low 16-bits of the general-purpose
register, so that the most significant addressed byte in memory appears in bits [15:8] of the ARM
register and bits [31:16] replicate the sign bit in bit 15, as Figure 4-7 on page 4-9 shows.
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Unaligned and Mixed-endian Data Access Support
Memory
7 0
Address
A[31:0]
B0 msbyte
+1 B1 lsbyte

Figure 4-5 Load unsigned halfword, big-endian

Memory
7 0
Address
A[31:0]
b0 lsbyte
+1 b1 msbyte

Figure 4-6 Load signed halfword, little-endian

Register
31 23 15 7
0 0 B0 B1
Register
31 23 15 7
se1 se1 b1 b0
0
0
4-8