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7.1
About the level one memory system
ARM DDI 0301H
ID012310
The processor level one memory system consists of:
•
separate Instruction and Data Caches in a Harvard arrangement
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separate Instruction and Data Tightly-Coupled Memory (TCM) areas
•
a DMA system for accessing the TCMs
•
a Write Buffer
•
two MicroTLBs, backed by a main TLB.
Each cache line can contain Secure or Non-secure data. In parallel with each of the caches is an
area of dedicated RAM on both the instruction and data sides. These regions are referred to as
TCM. You can implement 0, 1 or 2 TCMs on each of the Instruction and Data sides.
You can configure each TCM to contain Secure or Non-secure data. Each TCM has a dedicated
base address that you can place anywhere in the physical address map, and does not have to be
backed by memory implemented externally. The Instruction and Data TCMs have separate base
addresses. A DMA mechanism can access TCMs and this enables loads from or stores to
another location in memory while the processor core is running.
The MMU provides the facilities required by sophisticated operating systems to deliver
protected virtual memory environments and demand paging. It also supports real-time tasks
with features that provide predictable execution time.
A full MMU handles address translation for each of the instruction and data sides. The MMU is
responsible for protection checking, address translation, and memory attributes, some of which
can be passed to the level two memory system. The cache stores each Non-secure memory
region attribute, NS attribute, along with each cache line as an NS Tag.
The processor caches memory translations in MicroTLBs for each of the instruction and data
sides and for the DMA, with a single main TLB backing the MicroTLBs.
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Level One Memory System
7-2
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