Table 3-144 System Validation Operations Register Functions - ARM ARM1176JZF-S Technical Reference Manual

3.2.56 c15, System Validation Operations Register
ARM DDI 0301H
ID012310
The reset, interrupt, and fast interrupt counters reuse the Cycle Count Register, Count Register
0 and Count Register 1 of the System performance monitor registers respectively, see System
performance monitor on page 3-10. You must not use the System Validation Count Register
when the System Performance Monitor Registers are in use.
The reset, interrupt, and fast interrupt counters are read/write. The external debug request
counter is write only. Attempts to read the external debug request counter return
regardless or the actual value of the counter.
The purpose of the System Validation Operations Register is to start and stop system validation
counters to trigger a system validation event.
The System Validation Operations Register is:
• in CP15 c15
• a 32 bit read/write register common to the Secure and Non-secure worlds
• accessible in user and privileged modes.
The System Validation Operations Register consists of one 32-bit register that performs 16
functions. Table 3-144 lists the arrangement of the functions in this group.
CRn Opcode_1 CRm
c15 0 c13
c15 1 c13
c15 2 c13
c15 3 c13
A write to the System Validation Operations Register with a combination of Opcode_1 and
Opcode_2 that Table 3-144 does not list has no effect. A read from the System Validation
Operations Register returns
The reset value of this register is 0.
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Table 3-144 System Validation Operations Register functions

Opcode_2 R/W Operation
1 W Start reset counter
2 W Start interrupt counter
3 W Start reset and interrupt counters
4 W Start fast interrupt counter
5 W Start reset and fast interrupt counters
6 W Start interrupt and fast interrupt counters
7 W Start reset, interrupt and fast interrupt counters
0-7 W Start external debug request counter
1 W Stop reset counter
2 W Stop interrupt counter
3 W Stop reset and interrupt counters
4 W Stop fast interrupt counter
5 W Stop reset and fast interrupt counters
6 W Stop interrupt and fast interrupt counters
7 W Stop reset, interrupt and fast interrupt counters
0-7 W Stop external debug request counter
.
0x00000000
System Control Coprocessor
0x00000000
3-142