Table of Contents
Advertisement
22.6
Invalid Operation exception
Instruction
FADD
FSUB
FCMPE/FCMPEZ
FMUL/FNMUL
FDIV
FMAC/FNMAC
FMSC/FNMSC
FSQRT
FTOUI
FTOSI
a. In flush-to-zero mode, a subnormal input is treated as a positive zero for detecting an Invalid Operation exception.
22.6.1
Exception enabled
ARM DDI 0301H
ID012310
An operation is invalid if the result cannot be represented, or if the result is not defined.
Table 22-4 lists the operand combinations that produce Invalid Operation exceptions. In
addition to the conditions in Table 22-4, any CDP instruction other than FCPY, FNEG, or FABS
causes an Invalid Operation exception if one or more of its operands is an SNaN. See Table 20-1
on page 20-4.
Invalid Operation exceptions
(+infinity) + (–infinity) or (–infinity) + (+infinity).
(+infinity) – (+infinity) or (–infinity) – (–infinity).
Any NaN operand
Zero × ±infinity or ±infinity × zero.
Zero/zero or infinity/infinity.
Any condition that can cause an Invalid Operation exception for FMUL or FADD can cause an
Invalid Operation exception for FMAC and FNMAC. The product generated by the FMAC or
FNMAC multiply operation is considered in the detection of the Invalid Operation exception for the
subsequent sum operation.
Any of the conditions that can cause an Invalid Operation exception for FMUL or FSUB can cause
an Invalid Operation exception for FMSC and FNMSC. The product generated by the FMSC or
FNMSC multiply operation is considered in the detection of the Invalid Operation exception for the
subsequent difference operation.
Source is less than 0.
Rounded result would lie outside the range 0 ≤ result < 2
Rounded result would lie outside the range –2
Setting the IOE bit, FPSCR[8], enables Invalid Operation exceptions.
The VFP11 coprocessor causes a bounce to support code for all the invalid operation conditions
that Table 22-4 lists. Any arithmetic operation involving an SNaN also causes a bounce to
support code. The VFP11 coprocessor detects most Invalid Operations exceptions conclusively
but some are detected based on the possibility of an invalid operation. The potentially invalid
operations are:
•
FTOUI with a negative input. A small negative input might round to a zero, and this is not
an invalid condition.
•
A float-to-integer conversion with a maximum exponent for the destination integer and
any rounding mode other than round-towards-zero. The impact of rounding is unknown
in the Execute 1 stage.
•
An FMAC family operation with an infinity in the A operand and a potential product
overflow when an infinity with the sign of the product would result in an invalid condition.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Table 22-4 Possible Invalid Operation exceptions
a
a
32
≤ result < 2
31
VFP Exception Handling
.
31
.
22-13
Hide quick links:
Advertisement
Table of Contents
