Page 1 985 University Avenue Kanagawa Los Gatos 213 Japan CA 95030 USA Telephone: +81 44 850 1301 Telephone: +1 408 399 5199 Facsimile: +81 44 850 1308 Facsimile: +1 408 399 8854 Email: info@armltd.co.uk Email: info@arm.com World Wide Web address: http://www.arm.com Open Access...
Page 2 This document is intended only to assist the reader in the use of the product. ARM Ltd shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 3: Table Of Contents
Expanding and Monitoring the ASB Expanding the ASB Building an ASB Master Expansion Board Building an ASB Slave Expansion Board ASB Timing on the ARM Development Board ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 4 Page iv Wednesday, July 22, 1998 9:18 AM Contents Expanding and Monitoring the APB APB Expansion Interface Building an APB Slave Expansion Board APB Timing on the ARM Development Board The EmbeddedICE Interface EmbeddedICE Interface The Logic Analyser Interface ARM HP Inverse Assembler...
Page 5 Processor in PGA Package EmbeddedICE Interface Summary of Programmable Devices Programmable Devices Summary of Jumpers and Links Overview Surface Mount Links Standard 2-pin Links Link Fields DIP Switches Mechanical Information ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 6 hrg.book Page vi Wednesday, July 22, 1998 9:18 AM...
Page 7: Introduction
Page 1 Wednesday, July 22, 1998 9:18 AM Introduction This manual provides hardware reference information on the ARM Development Board. For information on connecting the board to a host computer and using the software development tools, please refer to the companion manual Target Development System User Guide (ARM DUI 0061) .
Page 8: Using This Manual
Appendix D is a summary of the switches, jumpers and links Appendix E is a mechanical drawing of the ARM Development Card 1.1.1 Related Documentation You may find it useful to refer to the following documents:...
Page 9: Useful Contacts
Introduction Useful Contacts 1.3.1 Contacting ARM Further information is available from ARM. All schematics (ORCAD), PLD and VHDL binary files and latest release notes are available from our world wide web servers at: http://www.arm.com If you require PDL descriptions or have difficulty accessing our web page, please email: upgrades@arm.com...
Page 10: Glossary
NISA NISA ( not-ISA ) is ARM’s description of the bus that connects the Advanced System Bus ( ASB ) to some standard peripheral devices such as the serial/parallel ports and PC card controller.
Page 11 Introduction A programmable array logic ( PAL ) device is a example of a programmable logic device ( PLD ). The PAL used on the ARM Development Card is a PALCE22V10. This has up to 22 inputs, ten outputs and ten programmable macrocells. As it is based on electrically erasable (EE) technology, it is reprogrammable.
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Page 13: Board Overview
Page 1 Wednesday, July 22, 1998 9:18 AM Board Overview This chapter describes each of the main blocks of the ARM Development Board. Overview of the ARM Development Board An Overview of the Board ARM Development Board (ARM7TDMI Version)
Page 14: Overview Of The Arm Development Board
Because the processor in the system is little more than ARM core it is possible to use an in- circuit emulator (ICE). This enables a system design to be tested and debugged at the processor level.
Page 15: An Overview Of The Board
2.2.1 Board architecture A convenient way to view the ARM Development Board is as a sample microcontroller with its support peripherals constructed from discrete devices. The bus master, system modules, APB bridge and peripherals, on-chip RAM and external bus interfaces form the heart of a microcontroller.
Page 16 External Bus I/F 32K x 32 Test SRAM DRAM PCMCIA 0-8 M 512K 128K x 32 SIMM Parallel + Serial Port Figure 2-1: Overview of the ARM Development Board ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 17: Circuit Descriptions
Page 1 Wednesday, July 22, 1998 9:18 AM Circuit Descriptions This chapter describes the circuits of the ARM Development Board. Overview of Schematics ARM Development Board ARM7TDMI Processor Daughter Board 3-26 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide...
Page 18: Overview Of Schematics
Circuit Descriptions Overview of Schematics The board has been designed to allow an AMBA bus master (such as an ARM7TDMI test chip) to be mounted on daughter board. The daughter board is an integral part of the ARM Development Board, although the daughter board supplied could be replaced with another AMBA master, such as an in-circuit emulator.
Page 19 The daughter board schematics for the supplied system are included in Appendix B, Daughter Board Schematics . The daughter board (or header) is connected to the ARM Development Board by four 60-way connectors. This allows different bus masters to be connected, including in-circuit emulators.
Page 20: Arm Development Board
The board is designed to function at 5V so that high-speed programmable logic devices can be used. The ARM processor is a 3.3V component and so needs to be protected from high logic levels. This is accomplished through use of level-convertor ICs. A 3.3V supply is generated on board from a 5V supply for use by the ARM processor and the synchronous SRAM (a 3.3V part with 5V tolerant I/O).
Page 21 The NISACLK is used to drive the NISA bus devices. This is a 32MHz clock signal, derived from CLK32MHZ, selected by a surface mount link (LK1). The CLK24MHZ output from (U5) is not normally used. ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C...
Page 22 SEL2 on/off see table below SEL3 on/off see table below Table 3-1: S1 Switch position Frequency (MHz SEL3 SEL2 SEL1 SEL0 SYSCLK SYSCLK2X Table 3-2: Switch positions ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 23 SRAM and DRAM controllers to enable big-endian style writes. There is no support for EPROMs that have been programmed big-endian. The BIGEND signal is also routed to the ARM processor. ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C...
Page 24 Because it is a pipelined device, the data is available to be read two clock cycles after the address is latched. In an ARM system, the data needs to be available in the clock cycle following the address. Therefore, by running the device at twice the system clock frequency, the data is read out in the correct system cycle.
Page 25 CYC[1:0] on page 3-10 shows pulse widths for various settings of CYC[1:0]. The write-enable strobe length (for FLASH only), is always the number of cycles minus one. Note ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 26 • write enable To connect such a peripheral to the ARM Development Board, disconnect any EPROM or FLASH devices and wire up the peripheral to the appropriate socket using a transition header. If you need to support EPROM or FLASH and a peripheral, some modification of the controller may be necessary.
Page 27 The basic memory size for all these modules is determined by the two presence-detect bits (PD1, PD0) with the addition of two pull-up resistors on the board. Only Slot A presence-detect is used. ARM Development Board (ARM7TDMI Version) 3-11 Hardware Reference Guide...
Page 28 The controller partitions the memory space into two logical banks of 256KB. The banks are called bank 0 and bank 1 and each has individual select lines for size and speed. 3-12 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C...
Page 29 8-bit 5 cycle (250ns @ 20MHz) memory (EPROM emulation) bank 1 16-bit 2 cycle (100ns @ 20MHz) memory (standard SRAM). Switch Name Position B0CYC0 B0CYC1 B0SIZ0 B0SIZ1 B1CYC0 B1CYC1 B1SIZ0 B1SIZ1 Table 3-7: Switches ARM Development Board (ARM7TDMI Version) 3-13 Hardware Reference Guide ARM DUI 0017C Open Access...
Page 30 • serial and parallel I/O port block • PC card (PCMCIA) interface block Details of these blocks can be found in the following sections. 3-14 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 31 Centronics type parallel printer port. This device is pin and functionally compatible with the VL16C552 and the WD16C552. In order to program the device you are advised to obtain a data sheet for one of these devices. Please contact ARM if you have any problems obtaining the datasheet.
Page 32 LED PP1 This information is summarized in Table 3-10: LED’s and read switches t: 13-14 LED PP2 15-16 LED PP3 Table 3-10: LED’s and read switches 3-16 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 33 Default INT TYPE latched or ACK mode latched DIRN parallel port direction BIDEN select LK10 ENABLE INT enable switch interrupt disabled enabled Table 3-11: Link summary ARM Development Board (ARM7TDMI Version) 3-17 Hardware Reference Guide ARM DUI 0017C Open Access...
Page 34 In order to program the controller, you are advised to obtain a data sheet from the manufacturer. Please contact ARM if you have any problems obtaining a data sheet. It is a complex device and a description of its internal function is outside the scope of this document.
Page 35 HIGH Z Note The signal names for slot A are prefixed by A_. The signal names for slot B are prefixed by B_. ARM Development Board (ARM7TDMI Version) 3-19 Hardware Reference Guide ARM DUI 0017C Open Access...
Page 36 P_SELCT, P_SELIC and P_SELRPC, which are the select lines for the functions above, there is also a P_SELEX line which can be used to select user implemented functions. If you wish to reprogram the FPGA for your own use then contact ARM for VHDL descriptions of this device.
Page 37 REMAP selects normal or reset memory map AS REQUIRED Table 3-13: FPGA outputs See Target Development System User Guide (ARM DUI 0061) for further details on the REMAP signal. ARM Development Board (ARM7TDMI Version) 3-21 Hardware Reference Guide...
Page 38: Interrupt Controller
The schematic shows one 16-bit address latch (U34) and two 16-bit data buffers (U35 and U36) that are used to connect the ASB to the memory devices. These devices are controlled by the SRAM and DRAM ASB slaves. 3-22 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 39 Table 3-14: LK17 For full details of the test interface refer to the AMBA Specification (ARM IHI 001). 3.2.18 Master Header Connectors and Level Convertors This schematic is shown in A.20 Master Header Connecters and Level Converters on page A-21.
Page 40 SRAM at the bottom of the address map. Name Description Options Default LK18 REMAP driven or always high out=high, in=driven Table 3-15: LK18 3-24 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 41 D_SELASB[1:0] are available. To enable these lines drive the signals nENASB[1:0] LOW. If you are planning to build external expansion devices for the ASB, refer to Chapter 4, Expanding and Monitoring the ASB for further details. ARM Development Board (ARM7TDMI Version) 3-25 Hardware Reference Guide ARM DUI 0017C...
Page 42: Arm7Tdmi Processor Daughter Board
Processor in PGA package This schematic is shown in B.7 Processor in PGA Package on page B-8. This schematic shows the ARM7TDMI test chip in a PGA package. It is identical in all other respects to the QFP packaged device.
Page 43 This schematic is shown in B.5 AMBA Bus Master Veneer on page B-6. In order to turn an ARM processor (such as the ARM7TDMI test chip) into an AMBA bus master an AMBA veneer is required. This function is performed by the MACH215 device (U2).
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Page 45: Expanding And Monitoring The Asb
This chapter describes how to expand and monitor the ASB. Expanding the ASB Building an ASB Master Expansion Board Building an ASB Slave Expansion Board ASB Timing on the ARM Development Board ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C...
Page 46: Expanding The Asb
Page 2 Wednesday, July 22, 1998 9:18 AM Expanding and Monitoring the ASB Expanding the ASB Note Please refer to the AMBA Specification (ARM IHI 0001) for a detailed description of the signals mentioned in this section. 4.1.1 Headers and pinout The ASB expansion interface comprises six 20-way box headers, horizontally mounted along the top edge of the development card.
Page 47 B_RES[2] D_SELNISA D_SELAPB B_RES[1] B_RES[0] nFIQSRC nENASB[1] B_PROT[1] B_PROT[0] nENASB[0] nINTASB[1] B_TRAN[1] B_TRAN[0] nINTASB[0] A_GNT002 B_SIZE[1] B_SIZE[0] A_GNT001 A_REQ002 B_WRITE A_REQ001 Figure 4-3: Pods 11 and 12 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 48 ASB select APB bridge D_SELNISA ASB select NISA bridge nINTASB[1:0] interrupt sources, active low, level sensitive nFIQSRC fast interrupt source, active low, level sensitive Table 4-1: ASB signals ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 49 ASB expansion request signal 1 A_REQ002 ASB expansion request signal 2 A_GNT001 ASB expansion grant signal 1 A_GNT002 ASB expansion grant signal 2 Table 4-1: ASB signals (Continued) ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 50: Building An Asb Master Expansion Board
A master can issue interrupts to the system CPU through the following: nINTASB[1:0] interrupt sources nFIQSRC fast interrupt source An expansion master cannot receive interrupts from other devices in the system. Note ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 51: Building An Asb Slave Expansion Board
B_LAST signals the last transfer in a burst If the slave generates interrupts: nINTASB[1:0] one or more of these IRQ sources nFIQSRC possibly the FIQ source ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 52: Asb Timing On The Arm Development Board
The AMBA specification does not specify bus timing, as this depends upon the technology used. For expansion on the ARM Development Board, it is important to have some timing guidelines. To assist with this, the following timings have been defined:...
Page 53 B_WAIT setup to B_CLK rising Tsrl B_LAST setup to B_CLK rising Tsre B_ERROR setup to B_CLK rising Tdata B_D setup to B_CLK falling Table 4-2: Sample timings ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 54 hrg.book Page 10 Wednesday, July 22, 1998 9:18 AM...
Page 55: Expanding And Monitoring The Apb
Expanding and Monitoring the APB The ARM Development Board implements an APB with full 32-bit address and data buses. In a typical system, these buses may well be narrower; the APB slaves only use 16 data lines and nine address lines. Full 32-bit support is provided for flexibility when expanding the APB.
Page 56: Apb Expansion Interface
Page 2 Wednesday, July 22, 1998 9:18 AM Expanding and Monitoring the APB APB Expansion Interface Note Please refer to the AMBA Specification (ARM IHI 0001) for a detailed description of the signals mentioned in this section. 5.1.1 Headers and pinout The APB expansion interface comprises six 20-way box headers horizontally mounted along the bottom edge of the development card.
Page 57 Figure 5-2: Pods 3 and 4 POD5 POD6 P_STB nINTAPB[2] nINTAPB[1] nINTAPB[0] B_RES[1] B_RES[2] nFIQSRC B_RES[0] P_SELIC P_SELRC P_SELCT P_SELEX P_WRITE Figure 5-3: Pods 5 and 6 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 58 APB select signal for reset/pause controller P_SELCT APB select signal for counter/timers P_SELEX APB select signal for expansion device P_WRITE APB read/write signal Table 5-1: APB signals ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 59: Building An Apb Slave Expansion Board
5.2.2 Interrupts If the slave generates interrupts: nINTAPB[2:0] one or more of these IRQ sources nFIQSRC possibly the FIQ source ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 60: Apb Timing On The Arm Development Board
The AMBA specification does not specify bus timing, as this depends upon the technology used. For expansion on the ARM Development Board it is important to have some timing guidelines. To assist with this, the following timings have been defined:...
Page 61 P_D hold from P_STB falling (write) Tpdr P_D setup to P_STB falling (read) Tpdz P_D hold from P_STB falling (read) B_CLK falling to P_STB falling Table 5-2: Sample timings ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 62 hrg.book Page 8 Wednesday, July 22, 1998 9:18 AM...
Page 63: The Embeddedice Interface
Page 1 Wednesday, July 22, 1998 9:18 AM The EmbeddedICE Interface This chapter describes how the EmbeddedICE interface connects to the ARM Development Board. EmbeddedICE Interface ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 64: Embeddedice Interface
Page 2 Wednesday, July 22, 1998 9:18 AM The EmbeddedICE Interface EmbeddedICE Interface A debuggable ARM processor (such as ARM7TDMI) on the ARM Development Board can be controlled through its JTAG port using the EmbeddedICE interface. The EmbeddedICE interface is packaged separately from the ARM Development Board.
Page 65 Test mode select Test clock Test data out nRSTOUT unused As pin 1 2, 4, 6, 8, 10, 14 System ground Table 6-1: EmbeddedICE interface connector pins ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 66 hrg.book Page 4 Wednesday, July 22, 1998 9:18 AM...
Page 67: The Logic Analyser Interface
This chapter describes the features of the ARM Development Card that facilitate code development and debugging. In most cases, you can download code and debug it using the ARM toolkit, in combination with either a debug monitor resident on the board or an EmbeddedICE interface. However, you sometimes need to use a logic analyser so you can debug code in real time.
Page 68: Arm Hp Inverse Assembler
ARM have developed an inverse assembler for use with HP logic analyzers to enable disassembly of the code. A set of six 2-way box headers are provided on the ARM Development Board for this purpose (POD 7-12). A further set is mounted on the ARM TDMI Daughter Board.
Page 69 MAS[1] MAS[0] nM[4] nM[3] nM[2] DBGACK nMREQ ABORT nTRANS LOCK nIRQ nFIQ TRAN[1] TRAN[0] nRESET PWAIT TBIT nCPI Figure 7-3: Pods 5 and 6 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 70 TRAN[1:0] processor BC[1:0] (equivalent to B_TRAN[1:0]) co-processor absent co-processor busy nCPI co-processor instruction +3.3V system ground Table 7-1: Logic analyser pod signals ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 71: The Test Interface
Page 1 Wednesday, July 22, 1998 9:18 AM The Test Interface This chapter describes how to use the test interface. Introducing the Test Interface Connecting External Equipment to the Test Bus Test Interface Interconnections ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 72: Introducing The Test Interface
Using the test bus interface, you can gain control of the ASB in real time and perform manufacturing test and in-circuit diagnostics. On a circuit board this is not usually a problem, but the ARM Development Board is a board-level implementation of a typical ASIC, where it would not be possible to examine the internal connections.
Page 73: Connecting External Equipment To The Test Bus
8.2.2 Test vectors ARM has code that runs on a host computer and drives an I/O board. This code requires a test vector file as input. The test vector file is written to provide stimulus and check data that is read back from the test bus.
Page 74: Test Interface Interconnections
The Test Interface Test Interface Interconnections The following diagram explains the interconnections: T_CLK T_REQA T_REQB ASB control T_ACK T_D[15:0] B_A[15:0] B_D[15:0] B_A[31:0] T_D[31:16] B_D[31:0] Figure 8-2: Test interface interconnections ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 75: Programming The Apb Fpga
This chapter describes how to program the field programmable gate array ( FPGA ) on the ARM Development Board. Introduction Interrupt Controller Using the APB FPGA in Your Own Designs ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 76: Introduction
Page 2 Wednesday, July 22, 1998 9:18 AM Programming the APB FPGA Introduction The ARM Development Board has one Xilinx 4000 series field programmable gate array ( FPGA ). The FPGA is an array of configurable logic blocks ( CLBs ) and in/out blocks ( IOBs ).
Page 77: Interrupt Controller
Program this register with any value from 0x0 to 0xF. Source 0 is the external FIQ source which is an active low, level-sensitive input on the ASB and APB expansion connectors. This input is pulled up on the ARM Development Board. 9.2.2...
Page 78: Using The Apb Fpga In Your Own Designs
Table 9-2: Configuring the FPGA The serial PROM is an 8-pin DIL packaged device that can be programmed using a standard device programmer. The appropriate data file is generated using Xilinx proprietary tools. ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C...
Page 79 If the MODE[2:0] pins are not linked, the FPGA is in master-slave mode. In this mode the FPGA expects to be configured using the XChecker download cable. The XChecker cable must be connected to the special 9-pin header provided on the ARM Development Board. The individual wires of the XChecker cable are labelled to aid the connection.
Page 80 To download a configuration: Connect the XChecker download cable to a serial port on the host computer. Connect the other end to the ARM Development Board (see 9.3.2 Connecting the XChecker Cable on page 9-5). Send the bit file to the FPGA using the XChecker download cable by typing the following command on the host machine: xchecker filename.bit...
Page 81: Programming The Mach And Pal Devices
Page 1 Wednesday, July 22, 1998 9:18 AM Programming the MACH and PAL Devices This chapter briefly describes the methods for programming the MACH and PAL devices. 10.1 Reprogramming a Device 10-2 ARM Development Board (ARM7TDMI Version) 10-1 Hardware Reference Guide ARM DUI 0017C Open Access...
Page 82: Reprogramming A Device
PALASM from AMD All the designs for the ARM Development Board were completed using PALASM which is a low-cost proprietary tool from the device vendor AMD. If you use a different PLD design tool then it should not be too difficult to modify the PALASM description to suit your front end.
Page 83: Board Schematics
A.19 Test Interface Controller and Connecters A-20 A.20 Master Header Connecters and Level Converters A-21 A.21 System Modules (Arbiter and Decoder) A-22 A.22 ASB Expansion Connecters A-23 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 84: Card Outline Drawing
LK10 ENABLE INTERRUPT Title LK17 USE TEST INTERFACE Card Outline Drawi LK18 REMAP Size Document Number ALL DIMENSIONS IN INCHES EOI-0011B (DRAWING. Date: March 8, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 85: Top-Level Diagram
CB1 4JN OSC.SCH ASBEXP.SCH BOARD OUTLINE NISACLK1 Title ARM7T Development Board ( SPARE CLOCK POINTS B_CLK8 Size Document Number ARM EOI-0011B (CHAMP DRAWING.SCH Date: March 2, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 86: Power Supply
Vout = 1.25(1 + (R3/R2)) + .00005.R3 (c) ADVANCED RISC MACHIN Fulbourn Road Cherry Hinton Cambridge CB1 4JN Title Power Supply Size Document Number ARM EOI-0011B (POWER Date: February 26, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 87: Crystal Oscillator And Clock Distribution
CB1 4JN EXTERNAL CLOCK SOURCES Title 100n 100n 100n 100n 100n Crystal oscillator and clock DECOUPLING CAPACITORS Size Document Number ARM EOI-0011B (OSC. Date: March 8, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 88: Asb Slaves
OF 256K BYTES EACH nB_CLK3 nB_CLK3 Fulbourn Road Cherry Hinton EPROM.SCH Cambridge CB1 4JN SRAM.SCH Title ASB Slaves Size Document Number ARM EOI-0011B (ASBSLAV Date: February 26, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 89: On-Chip" Memory (Synchronous Sram
FULBOURN ROAD CHERRY HINTON CAMBRIDGE CB1 4JN 100n 100n 100n 100n 100n Title ’On chip’ (synchronous SRA Size Document Number EOI-0011B (ONCHIP.S Date: February 26, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 90: Eprom/Flash Asb Slave
CHERRY HINTON CAMBRIDGE CB1 4JN Title 100n 100n 100n 100n 100n 100n 100n 100n EPROM/FLASH ASB Sla Size Document Number EOI-0011B (EPROM.S Date: February 26, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 91: Dram Asb Slave
CB1 4JN Title 100n 100n 100n 100n USE IDENTICAL SIMMS IF BOTH SLOTS USED DRAM ASB Slave Size Document Number ARM EOI-0011B (DRAM. Date: February 26, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 92: Sram Asb Slave
Cambridge M_D3 CB1 4JN 100n 100n 100n 100n 100n 100n SRAM128K8-20 Title SRAM ASB Slave Size Document Number ARM EOI-0011B (SRAM. Date: February 26, 1996 Sheet A-10 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 93: Apb And Nisa Bridge
CB1 4JN - 1 cycle Title 100n 100n 100n 100n APB and NISA Bridg MONITOR POINT Size Document Number EOI-011B (ASBNISA.S Date: February 26, 1996 Sheet A-11 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 94: Nisa Bus Peripherals
SUPERIO.SCH (C) ADVANCED RISC MAC FULBOURN ROAD CHERRY HINTON CAMBRIDGE CB1 4JN Title NISA Bus Periphera Size Document Number EOI-0011B (NISABUS. Date: February 26, 1996 Sheet A-12 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 95: Serial And Parallel Ports
CHERRY HINTON CAMBRIDGE CB1 4JN Title 100n 100n 100n 100n 100n 100n Serial and Parallel P Size Document Number EOI-0010B (SUPERIO. Date: March 8, 1996 Sheet A-13 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 96: Pc Card Interface
YELLOW LEDPCA CB1 4JN U24C Title R135 PC-Card (PCMCIA) Interface an B_GPIO Size Document Number 470R EOI-0011B (PCMCIA.S 74HCT14 YELLOW LEDPCB Date: February 26, 1996 Sheet A-14 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 97: Pc Card Connecters And Power Supply
CB1 4JN Title 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n PC-Card Connector and Powe Size Document Number EOI-0011B (CARDCON. Date: February 26, 1996 Sheet A-15 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 98: Apb Slaves
APB Slaves 100n 100n 100n 100n LINK-4 Insert links 3-4, 5-6, 7-8 Size Document Number to enable serial PROM ARM EOI-0011B (APBSLAV Date: February 26, 1996 Sheet A-16 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 99: Apb Expansion Connecters
(C) ADVANCED RISC MAC FULBOURN ROAD PULLUPS ON INTERRUPTS CHERRY HINTON CAMBRIDGE CB1 4JN Title APB Expansion Connec Size Document Number EOI-0011B (APBEXP.S Date: February 26, 1996 Sheet A-17 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 100: Apb Buffers
C117 C110 C111 C112 C113 Title 100n 100n 100n 100n 100n 100n 100n 100n APB Buffers Size Document Number EOI-0011B (APBBUF.S Date: February 26, 1996 Sheet A-18 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 101: Memory Address And Data Buffers
C123 C118 C119 C120 C121 Title 100n 100n 100n 100n 100n 100n Address and Data Buf Size Document Number EOI-0011B (MEMBUF.S Date: February 26, 1996 Sheet A-19 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 102: Test Interface Controller And Connecters
100n 100n OUT = TIC disabled (default) = TIC enabled Title Test Interface Controller an Size Document Number ARM EOI-0011B (TIC. Date: February 26, 1996 Sheet A-20 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 103: Master Header Connecters And Level Converters
C102 R190 C103 R191 Title ARM Master Header and Level Size Document Number ARM EOI-0011B (MASTER LEVEL SHIFTER INDIVIDUAL POWER SUPPLIES Date: February 26, 1996 Sheet A-21 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 104: System Modules (Arbiter And Decoder
C105 C106 C107 C108 CHERRY HINTON 100n 100n 100n 100n CAMBRIDGE CB1 4JN Title System Modules Size Document Number EOI-0011B (SYSMODS. Date: February 26, 1996 Sheet A-22 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 105: Asb Expansion Connecters
(C) ADVANCED RISC MAC FULBOURN ROAD CHERRY HINTON CAMBRIDGE CB1 4JN Title ASB Expansion Connec Size Document Number EOI-0011B (ASBEXP.S Date: February 26, 1996 Sheet A-23 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 106: B Daughter Board Schematics
Card Outline Drawing Top-level Diagram Header Connecters Logic Analyser Connecters AMBA Bus Master Veneer Processor in QFP Package Processor in PGA Package EmbeddedICE Interface ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 107: B.1 Card Outline Drawing
ALL DIMENSIONS IN INCHES (C) ADVANCED RISC MAC FULBOURN ROAD CHERRY HINTON CAMBRIDGE CB1 4JN Title Header Card Outline Dr Size Document Number EOI-0016B (DRAWING. Date: June 14, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 108: B.2 Top-Level Diagram
BOARD OUTLINE Title VDD is system 3V3 ARM7T Development Board He VSS is system ground Size Document Number ARM EOI-0016B (CHAMPQF DRAWING.SCH Date: June 14, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 109: B.3 Header Connecters
Cambridge 560R CB1 4JN DO NOT FIT Title GNTARM GNTARM Processor and header con nTRST Size Document Number nTRST ARM EOI-0016B (CPUHEA Date: June 14, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 110: B.4 Logic Analyser Connecters
CON20AP (c) ADVANCED RISC MACHIN Fulbourn Road Cherry Hinton Cambridge CB1 4JN Title Logic Analyser connec Size Document Number ARM EOI-0016B (LAPODS Date: June 14, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 111: B.5 Amba Bus Master Veneer
Default B-C Default A-C Fulbourn Road Cherry Hinton Cambridge CB1 4JN Title AMBA Bus Master Ven Size Document Number ARM EOI-0016B (AMBAPL Date: June 14, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 112: B.6 Processor In Qfp Package
(C) ADVANCED RISC MAC MABE FULBOURN ROAD CHERRY HINTON CAMBRIDGE nTRST nTRST CB1 4JN Title Processor in QFP pac Size Document Number ARM EOI-0016B (PROCQF Date: June 14, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 113: B.7 Processor In Pga Package
3045 MABE FULBOURN ROAD CHERRY HINTON CAMBRIDGE nTRST nTRST CB1 4JN Title Processor in PGA pac Size Document Number ARM EOI-0012 (PROCPGA Date: September 13, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 114: B.8 Embeddedice Interface
(c) ADVANCED RISC MACHIN Fulbourn Road Cherry Hinton Cambridge CB1 4JN Title EmbeddedICE Interfa Size Document Number ARM EOI-0016B (EICE. Date: June 14, 1996 Sheet ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 115: Summary Of Programmable Devices
Page 1 Wednesday, July 22, 1998 9:18 AM Summary of Programmable Devices This appendix summarizes the available programmable devices. Programmable Devices ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 116 EFI-0024 MACH210A-7 APBIF EFI-0025 MACH231-7 APBPER EFI-0026 XC17128D serial PROM EFI-0027 MACH210A-7 ARBRES8 EFI-0028 MACH210A-7 DECODER EFI-0029 MACH210A-7 Table C-1: Programmable devices Note U28 is not re-programmable. ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 117 C.1.3 MACH and PALCE All MACH and PALCE devices can be reprogrammed. The functionality of these devices was designed using PALASM. The PALASM source is available from ARM, as described in 1.3 Useful Contacts on page 1-3. C.1.4 FPGA The FPGA is programmed by serial PROM (U28). To reprogram the device you need to replace this PROM with a new one.
Page 118 hrg.book Page 4 Wednesday, July 22, 1998 9:18 AM...
Page 119: D Summary Of Jumpers And Links
Page 1 Wednesday, July 22, 1998 9:18 AM Summary of Jumpers and Links This appendix summarises the jumpers and links. Overview Surface Mount Links Standard 2-pin Links Link Fields DIP Switches ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 120: Overview
Page 2 Wednesday, July 22, 1998 9:18 AM Summary of Jumpers and Links Overview The ARM Development Card is configurable through the use of links, jumpers and switches. Each of these is described in detail in Chapter 3, Circuit Descriptions . This section summarises that information.
Page 121: Standard 2-Pin Links
ENABLE INT disable switch interrupt enable switch interrupt LK17 USETIC disable test interface enable test interface LK18 REMAP REMAP high REMAP driven Table D-2: Standard 2-pin links ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 122: D.4 Link Fields
MODE0 use download cable use serial PROM MODE1 use download cable use serial PROM MODE2 use download cable use serial PROM Table D-4: LK6, LK11, and LK16 ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 123: Dip Switches
3 Table D-7: S!, S2, and S3 Switch position Frequency (MHz) SEL3 SEL2 SEL1 SEL0 SYSCLK SYSCLK2X Table D-8: S1 switch positions ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...
Page 124 hrg.book Page 6 Wednesday, July 22, 1998 9:18 AM...
Page 125: E Mechanical Information
Page 1 Wednesday, July 22, 1998 9:18 AM Mechanical Information This appendix shows a mechanical drawing of the ARM Development Card with dimensions to help you to build add-on hardware. ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C...
Page 126 Mechanical Information ARM Development Board (ARM7TDMI Version) Hardware Reference Guide ARM DUI 0017C Open Access...

ARM ARM7TDMI Hardware Reference Manual

1 Introduction

2 Board Overview

3 Circuit Descriptions

4 Expanding and Monitoring the ASB

ARM Development Board (ARM7TDMI Version)

Hardware Reference Guide

5 Expanding and Monitoring the APB

6 The Embeddedice Interface

7 The Logic Analyser Interface

8 The Test Interface

9 Programming the APB FPGA

10 Programming the MACH and PAL Devices

Board Schematics

ARM Development Board (ARM7TDMI Version)

Hardware Reference Guide

Open Access

B Daughter Board Schematics

Summary of Programmable Devices

D Summary of Jumpers and Links

E Mechanical Information

ARM Development Board (ARM7TDMI Version) Hardware Reference Guide

Quick Links

Related Manuals for ARM ARM7TDMI

Summary of Contents for ARM ARM7TDMI

Table of Contents