Interrupt Signals, Including Vic Interface; Table A-4 Interrupt Signals - ARM ARM1176JZF-S Technical Reference Manual

A.4

Interrupt signals, including VIC interface

ARM DDI 0301H
ID012310
Table A-4 lists the interrupt signals, including those used with the VIC interface.
Note
All the outputs listed in this section have their reset values in Standby mode.
Name
INTSYNCEN
IRQACK
IRQADDR[31:2]
IRQADDRV
IRQADDRVSYNCEN
nFIQ
a
nIRQ
a
nPMUIRQ
nDMAIRQ
nDMASIRQ
nDMAEXTERRIRQ
a. Because this signal is level-sensitive, to generate an interrupt you must ensure it is held LOW until the
processor sends a suitable interrupt response.
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Direction Description
When HIGH, indicates that the internal nFIQ and nIRQ
Input
synchronizers are bypassed and the interface is synchronous
Output Interrupt acknowledge
Input Address of IRQ
Indicates IRQADDR is valid
Input
When HIGH, indicates that IRQADDRV synchronizer is
Input
bypassed and the interface is synchronous
Input Fast interrupt request
Input Interrupt request
Output Interrupt request from System Metrics
Output Non-secure DMA Interrupt
Output Secure DMA Interrupt
Output Not maskable error DMA Interrupt
Signal Descriptions

Table A-4 Interrupt signals

A-6