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ARM DDI 0301H
ID012310
•
32-bit assembled code of the instruction, instr, to be executed, for ITR[31:0].
2.
The following data is scanned out:
•
The value of the Ready flag, to be stored in stateout.
•
32 bits to be ignored. The ITR is write-only.
DATA <datain> [<stateout> [dataout]]
Go through Capture-DR, go to Shift-DR. Scan in a data item and scan out another one, go
through Update-DR. Either the DTR, scan chain 5, or the DSCR, scan chain 1, must be selected
when using this macro.
1.
If scan chain 5 is selected, scan in:
•
Any value for the nRetry or Valid flag. These bits are read-only.
•
Any value for the InstCompl flag. This bit is read-only.
•
32-bit datain value for rDTR[31:0].
2.
The following data is scanned out:
•
The contents of wDTR[31:0], to be stored in dataout.
•
If the DSCR[13] execute ARM instruction enable bit is set, the value of the Ready
flag is stored in stateout.
•
If the DSCR[13] execute ARM instruction enable bit is clear, the nRetry or Valid
flag, depending on whether EXTEST or INTEST is selected, is stored in stateout.
3.
If scan chain 1 is selected, scan in:
•
32-bit datain value for DSCR[31:0].
Stateout and dataout fields are not used in this case.
DATAOUT <dataout>
1.
Scan out a data value. DSCR, scan chain 1, and INTEST must be selected when using this
macro.
2.
If scan chain 1 is selected, scan out the contents of the DSCR, to be stored in dataout.
3.
The scanned-in value is discarded, because INTEST is selected.
REQ <address> <data> <nR/W> [<stateout> [dataout]]
Go through Capture-DR, go to Shift-DR, scan in a request and scan out the result of the former
one, go through Update-DR. Scan chain 7, and either INTEST or EXTEST, must be selected
when using this macro.
1.
Scan in:
•
7-bit address value for Address[6:0]
•
32-bit data value for Data[31:0]
•
1-bit nR/W value, 0 for read and 1 for write, for the Ready/nRW field.
2.
Scan out:
•
the value of the Ready/nRW bit, to be stored in stateout
•
the contents of the Data field, to be stored in dataout.
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Debug Test Access Port
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