Power Management - ARM ARM1176JZF-S Technical Reference Manual

1.6

Power management

ARM DDI 0301H
ID012310
The ARM1176JZF-S processor includes several micro-architectural features to reduce energy
consumption:
• Accurate branch and return prediction, reducing the number of incorrect instruction fetch
and decode operations.
• Use of physically tagged caches that reduce the number of cache flushes and refills, to
save energy in the system.
• The use of MicroTLBs reduces the power consumed in translation and protection
look-ups for each memory access.
• The caches use sequential access information to reduce the number of accesses to the Tag
RAMs and to unmatched data RAMs.
• Extensive use of gated clocks and gates to disable inputs to unused functional blocks.
Because of this, only the logic actively in use to perform a calculation consumes any
dynamic power.
• Optionally supports IEM. The ARM1176JZF-S is separated into three different blocks to
support three different power domains:
— all the RAMS
the core logic that is clocked by CLKIN and FREECLKIN
—
— four optional IEM Register Slices to have an asynchronous interface between the
Level 2 ports powered by VCore and clocked by CLKIN, and the AXI system
powered by VSoc and clocked by ACLK clocks, one for each port.
The ARM1176JZF-S processor support four levels of power management:
Run mode This mode is the normal mode of operation when the processor can use all its
functions.
Standby mode
This mode disables most of the processor clocks of the device, while processor
remains powered up. This reduces the power drawn to the static leakage current,
plus a tiny clock power overhead required to enable the processor to wake up from
the standby state. One of the following events cause a transition from the standby
mode to the run mode:
• an interrupt, either masked or unmasked
• a debug request, regardless of whether debug is enabled
• reset.
Shutdown mode
This mode powers down the entire processor. The processor must save all states,
including cache and TCM state, externally. The processor is returned to the run
state by the assertion of reset. The processor saves the states with interrupts
disabled, and finishes with a Data Synchronization Barrier operation. The
ARM1176JZF-S processor then communicates with the power controller that it is
ready to be powered down.
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Introduction
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