Table of Contents
Advertisement
22.3.1
Illegal instructions
ARM DDI 0301H
ID012310
8.
If the FP2V flag, FPEXC[28], is set and IXE, FPSCR[12], is clear, the FPINST2 register
contains another VFP instruction that was issued between the potentially exceptional
instruction and the trigger instruction. This instruction is executed by the support code in
the same manner as the instruction in the FPINST register. The FP2V flag must be cleared
before returning to user code. See Instruction registers, FPINST and FPINST2 on
page 20-18 for more on FPINST2.
9.
The support code finishes processing the potentially exceptional instruction and returns to
the program containing the trigger instruction. The ARM11 processor refetches the
trigger instruction from memory and reissues it to the VFP11 coprocessor. Unless another
bounce occurs, the trigger instruction is executed. Returning in this fashion is called
retrying the trigger instruction.
The support code can be written to use the VFP11 hardware for its internal calculations,
provided that:
•
recursive bounces are prevented or handled correctly
•
care is taken to restore the state of the original program before returning to it.
Restoring the state of the original program can be difficult if the original program was executing
in FIQ mode or in Undefined instruction mode. It is legitimate for support code to prevent or
restrict the use of VFP11 instructions in these two processor modes.
If there is not a potential floating-point exception from an earlier instruction, the current
instruction can still be bounced if it is architecturally Undefined in some way. When this
happens, the EX flag, FPEXC[31], is not set. The instruction that caused the bounce is contained
in the memory word pointed to by R14_undef – 4.
It is possible that both conditions for an instruction to be bounced occur simultaneously. This
happens when an illegal instruction is encountered and there is also a potential floating-point
exception from an earlier instruction. When this happens, the EX flag is set, and the support
code processes the potential exception in the earlier instruction. If and when it returns, it causes
the illegal instruction to be retried and the sequence of events that the paragraph above describes
occurs.
The following instruction types are architecturally Undefined. See ARM Architecture Reference
Manual, Rev E, Part C:
•
instructions with opcode bit combinations defined as reserved in the architecture
specification
•
load or store instructions with Undefined P, W, and U bit combinations
•
FMRX/FMXR instructions to or from a control register that is not defined
•
User mode FMRX/FMXR instructions to or from a control register that can be accessed
only in a privileged mode
•
double precision operations with odd register numbers.
Certain instruction types do not have architecturally-defined behavior and are Unpredictable:
•
load or store multiple instructions with a transfer count of zero or greater than 32, and any
combination of initial register and transfer count so that an attempt is made to transfer a
register beyond S31 for single-precision transfers, or D15 for double-precision transfers
•
a short vector instruction with a combination of precision, length, and stride that causes
the vector to wrap around and make more than one access to the same register
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
VFP Exception Handling
22-6
Hide quick links:
Advertisement
Table of Contents
