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3.1.3
MMU control and configuration
ARM DDI 0301H
ID012310
Some of the functionality depends on how you set external signals at reset.
System control and configuration behaves in three ways:
•
as a set of flags or enables for specific functionality
•
as a set of numbers, values that indicate system functionality
•
as a set of addresses for processes in memory.
The purpose of the MMU control and configuration registers is to:
•
allocate physical address locations from the Virtual Addresses (VAs) that the processor
generates.
•
control program access to memory.
•
designate areas of memory as either:
—
noncacheable
—
unbufferable
—
noncacheable and unbufferable.
•
detect MMU faults and external aborts
•
hold thread and process IDs
•
provide direct access to the TLB lockdown entries.
The MMU control and configuration registers consist of one 32-bit read-only register, one 32-bit
write-only register, and 22 32-bit read/write registers. Figure 3-2 on page 3-7 shows the
arrangement of registers in this functional group.
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System Control Coprocessor
3-6
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