Table 3-34 Instruction Set Attributes Register 3 Bit Functions; Table 3-35 Results Of Access To The Instruction Set Attributes Register 3 - ARM ARM1176JZF-S Technical Reference Manual

Field
Bits
name
[31:28] -
[27:24] -
[23:20] -
[19:16] -
[15:12] -
[11:8] -
[7:4] -
[3:0] -
ARM DDI 0301H
ID012310
Table 3-34 lists how the bit values correspond with the Instruction Set Attributes Register 3
functions.
Function
Indicates support for Thumb-2 extensions.
0x0 , no support in ARM1176JZF-S processors.
Indicates support for true NOP instructions.
, ARM1176JZF-S processors support NOP and the capability for additional NOP compatible
0x1
hints. ARM1176JZF-S processors do not support NOP16.
Indicates support for Thumb copy instructions.
, ARM1176JZF-S processors support Thumb MOV(3) low register ⇒ low register, and the CPY
0x1
alias for Thumb MOV(3).
Indicates support for table branch instructions.
, no support in ARM1176JZF-S processors.
0x0
Indicates support for synchronization primitive instructions.
0x2 , ARM1176JZF-S processors support:
• LDREX and STREX
• LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, and CLREX
Indicates support for SVC instructions.
, ARM1176JZF-S processors support SVC.
0x1
Indicates support for Single Instruction Multiple Data (SIMD) instructions.
0x3 , ARM1176JZF-S processors support:
PKHBT, PKHTB, QADD16, QADD8, QADDSUBX, QSUB16, QSUB8, QSUBADDX, SADD16,
SADD8, SADDSUBX, SEL, SHADD16, SHADD8, SHADDSUBX, SHSUB16, SHSUB8,
SHSUBADDX, SSAT, SSAT16, SSUB16, SSUB8, SSUBADDX, SXTAB16, SXTB16, UADD16,
UADD8, UADDSUBX, UHADD16, UHADD8, UHADDSUBX, UHSUB16, UHSUB8,
UHSUBADDX, UQADD16, UQADD8, UQADDSUBX, UQSUB16, UQSUB8, UQSUBADDX,
USAD8, USADA8, USAT, USAT16, USUB16, USUB8, USUBADDX, UXTAB16, UXTB16, and
the GE[3:0] bits in the PSRs.
Indicates support for saturate instructions.
, ARM1176JZF-S processors support QADD, QDADD, QDSUB, QSUB and Q flag in PSRs.
0x1
Table 3-35 lists the results of attempted access for each mode.

Table 3-35 Results of access to the Instruction Set Attributes Register 3

Secure Privileged
Read Write
Data Undefined exception
To use the Instruction Set Attributes Register 3 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c2
• Opcode_2 set to 3.
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Table 3-34 Instruction Set Attributes Register 3 bit functions

Non-secure Privileged
Read Write
Data Undefined exception
System Control Coprocessor
User
Undefined exception
3-41