ARM ARM1176JZF-S Technical Reference Manual page 116

ARM DDI 0301H
ID012310
STR R0, [R8,#AckFinished]
SUBS PC, R14, #4
...
FIQ2handler
STMIA R13, {R0-R3}
MOV R0, LR
MRS R1, SPSR
ADD R2, R13, #8
MRS R3, CPSR
BIC R3, R3, #0x1F
ORR R3, R3, #0x1B
MSR CPSR_c, R3
STMFD R13!, {R0, R1}
LDMIA R2, {R0, R1}
STMFD R13!, {R0, R1}
LDMDB R2, {R0, R1}
BIC R3, R3, #0x40
MSR CPSR_c, R3
... FIQs are now re-enabled, with original R2, R3, R14, SPSR on stack
... Include code to stack any more registers required, process the interrupt
... and unstack extra registers
ADR R2, #VICaddress
MRS R3, CPSR
ORR R3, R3, #0x40
MSR CPSR_c, R3
STR R0, [R2,#AckFinished]
LDR R14, [R13,#12] ; Original SPSR value
MSR SPSR_fsxc, R14
LDMFD R13!, {R2,R3,R14}
ADD R13, R13, #4
SUBS PC, R14, #4
...
The major problem with this is the length of time that FIQs are disabled at the start of the lower
priority FIQs. The worst-case interrupt latency for the FIQ1 interrupt occurs if a lower priority
FIQ2 has fetched its handler address, and is approximately:
• 3 cycles for the pipeline refill after the LDR PC instruction fetches the handler address
• + 24 cycles to get to and execute the MSR instruction that re-enables FIQs
• + 3 cycles to re-enter the FIQ exception
• + 5 cycles for the LDR PC instruction at FIQhandler
• = 35 cycles.
Note
FIQs must be disabled for the final store to acknowledge the end of the handler to the VIC.
Otherwise, more badly timed FIQs, each occurring close to the end of the previous handler, can
cause unlimited growth of the locked-down stack.
FIQs in the example system in ARMv6
Using the VIC and the new instructions, there is no longer any requirement for everything to go
through the single FIQ vector, and the changeover to a different stack occurs much more
smoothly. The code is:
FIQ1handler
... Include code to process the interrupt ...
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; = Abort mode number
; = F bit
; = F bit
Programmer's Model
2-43