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2.12.9
Interrupt latency example
ARM DDI 0301H
ID012310
This section gives an extended example to show how the combination of new facilities improves
interrupt latency. The example is not necessarily entirely realistic, but illustrates the main points.
To be simpler, this example applies for legacy code, that is for code that does not use any
TrustZone features. You can therefore assume the core only runs code in either Secure or
Non-secure world.
The assumptions made are:
1.
Vector Interrupt Controller (VIC) hardware exists to prioritize interrupts and to supply the
address of the highest priority interrupt to the processor core on demand. In the ARMv5
system, the address is supplied in a memory-mapped I/O location, and loading the address
acts as an entering interrupt handler acknowledgement to the VIC. In the ARMv6 system,
the address is loaded and the acknowledgement given automatically, as part of the
interrupt entry sequence. In both systems, a store to a memory-mapped I/O location is
used to send a finishing interrupt handler acknowledgement to the VIC.
2.
The system has the following layers:
Real-time layer
Architectural completion layer
Non real-time layer
3.
The corresponding exception priority structure is as follows, from highest to lowest
priority:
a.
FIQ1, highest priority FIQ
b.
FIQ2
c.
...
d.
FIQm, lowest priority FIQ
e.
Data Abort
f.
Prefetch Abort
g.
Undefined instruction
h.
SVC
i.
IRQ1, highest priority IRQ
j.
IRQ2
k.
...
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Contains handlers for a number of high-priority interrupts. These
interrupts can be prioritized, and are assumed to be signaled to the
processor core by means of the FIQ interrupt. Their handlers do not
use the facilities supplied by the other two layers. This means that
all memory they use must be locked down in the TLBs and caches.
It is possible to use additional code to make access to nonlocked
memory possible, but this example does not describe this.
Contains Prefetch Abort, Data Abort and Undefined instruction
handlers whose purpose is to give the illusion that the hardware is
handling all memory requests and instructions on its own, without
requiring software to handle TLB misses, virtual memory misses,
and near-exceptional floating-point operations, for example. This
illusion is not available to the real-time layer, because the software
handlers concerned take a significant number of cycles, and it is not
reasonable to have every memory access to take large numbers of
cycles. Instead, the memory concerned has to be locked down.
Provides interrupt handlers for low-priority interrupts. These
interrupts can also be prioritized, and are assumed to be signaled to
the processor core using the IRQ interrupt.
Programmer's Model
2-41
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