Table 3-2 Summary Of Cp15 Registers And Operations - ARM ARM1176JZF-S Technical Reference Manual

CRn Op1
c0 0
c1 0
ARM DDI 0301H
ID012310
CRm Op2 Register or operation
c0 0 Main ID
1 Cache Type
2 TCM Status
3 TLB Type
c1 0 Processor Feature 0
1 Processor Feature 1
2 Debug Feature 0
3 Auxiliary Feature 0
4 Memory Model Feature 0
5 Memory Model Feature 1
6 Memory Model Feature 2
7 Memory Model Feature 3
c2 0 Instruction Set Feature
Attribute 0
1 Instruction Set Feature
Attribute 1
2 Instruction Set Feature
Attribute 2
3 Instruction Set Feature
Attribute 3
4 Instruction Set Feature
Attribute 4
5 Instruction Set Feature
Attribute 5
6-7 Reserved
c3-c7 - Reserved
c0 0 Control
1 Auxiliary Control
2 Coprocessor Access Control
c1 0 Secure Configuration
1 Secure Debug Enable
2 Non-Secure Access Control
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Table 3-2 Summary of CP15 registers and operations

NS
S type
type
RO RO
RO RO
RO RO
RO RO
RO RO
RO RO
RO RO
RO RO
RO RO
RO RO
RO RO
RO RO
RO RO
RO RO
RO RO
RO RO
RO RO
RO RO
- -
- -
d R/W
R/W, B , X
R/W RO
R/W R/W
R/W NA
R/W NA
R/W RO
System Control Coprocessor
Reset
Page
value
page 3-20
a
0x41xFB76x
b page 3-21
0x10152152
c page 3-24
0x00020002
page 3-25
0x00000800
page 3-26
0x00000111
page 3-27
0x00000011
0x00000033 page 3-29
0x00000000 page 3-30
0x01130003 page 3-31
0x10030302 page 3-32
0x01222100 page 3-33
0x00000000 page 3-35
page 3-36
0x00140011
page 3-37
0x12002111
page 3-39
0x11231121
page 3-40
0x01102131
page 3-42
0x00001141
page 3-43
0x00000000
- -
- -
e page 3-44
0x00050078
page 3-48
0x00000007
page 3-51
0x00000000
page 3-52
0x00000000
page 3-54
0x00000000
page 3-55
0x00000000
3-14