16.16 Svc, Smc, Bkpt, Undefined, And Prefetch Aborted Instructions; Table 16-23 Svc, Bkpt, Undefined, Prefetch Aborted Instructions Cycle Timing Behavior - ARM ARM1176JZF-S Technical Reference Manual

16.16 SVC, SMC, BKPT, Undefined, and Prefetch Aborted instructions

ARM DDI 0301H
ID012310
This section describes the cycle timing behavior for SVC, SMC, Undefined Instruction, BKPT
and Prefetch Abort.
In all cases, the exception is taken in the WBex stage of the pipeline. SVC, SMC, and most
Undefined instructions that fail their condition codes take one cycle. A small number of
undefined instructions that fail their condition codes take two cycles. Table 16-23 lists the SVC,
SMC, BKPT, undefined, prefetch aborted instructions cycle timing behavior.

Table 16-23 SVC, BKPT, undefined, prefetch aborted instructions cycle timing behavior

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Cycle Timings and Interlock Behavior
Cycle
Instruction
s
SVC 8
SMC 8
BKPT 8
Prefetch Abort 8
Undefined Instruction 8
16-26