Table of Contents
Advertisement
3.2.32
c10, Memory region remap registers
ARM DDI 0301H
ID012310
The Invalidate TLB unlocked entries operation does not invalidate TLB entries in the lockdown
region.
Invalidate TLB Entry by MVA and Invalidate TLB Entry on ASID Match operations invalidate
any TLB entries that correspond to the MVA or ASID given in Rd, if they are in the lockdown
region or if they are in the set-associative region of the TLB. See c8, TLB Operations Register
on page 3-86 for a description of the TLB invalidate operations.
The victim automatically increments after any page table walk that results in a write puts an
entry into the lockdown part of the TLB.
To use the TLB Lockdown Register read or write CP15 with:
•
Opcode_1 set to 0
•
CRn set to c10
•
CRm set to c0
•
Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c10, c0, 0
MCR p15, 0, <Rd>, c10, c0, 0
Example 3-2 is a code sequence that locks down an entry to the current victim.
ADR r1,LockAddr
MCR p15,0,r1,c8,c7,1
MRC p15,0,R0,c10,c0,0
ORR R0,R0,#1
MCR p15,0,R0,c10,c0,0
LDR r1,[r1]
MRC p15,0,R0,c10,c0,0
BIC R0,R0,#1
MCR p15,0,R0,c10,c0,0
The purpose of the memory region remap registers is to remap memory region attributes
encoded by the TEX[2:0], C, and B bits in the page tables that the Data side, Instruction side,
and DMA use. For details of memory remap, see Memory region attributes on page 6-14.
The memory region remap registers are:
•
in CP15 c10
•
two 32-bit read/write registers banked for the Secure and Non-secure worlds:
—
the Primary Region Remap Register
—
the Normal Memory Remap Register.
•
accessible in privileged modes only.
These registers apply to all memory accesses and this includes accesses from the Data side,
Instruction side, and DMA. Table 3-99 on page 3-102 lists the purposes of the individual bits in
the Primary Region Remap Register. Table 3-101 on page 3-103 lists the purposes of the
individual bits in the Normal Memory Remap Register.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
; Read TLB Lockdown Register
; Write TLB Lockdown Register.
Example 3-2 Lock down an entry to the current victim
; set r1 to the value of the address to be locked down
; invalidate TLB single entry to ensure that
; LockAddr is not already in the TLB
; read the lockdown register
; set the preserve bit
; write to the lockdown register
; TLB misses, and entry is loaded
; read the lockdown register (victim
; increments)
; clear preserve bit
; write to the lockdown register
System Control Coprocessor
3-101
Hide quick links:
Advertisement
Table of Contents
