Coprocessor pipeline ................................................................................................................ 11-6
Token queue buffers ................................................................................................................. 11-9
Queue reading and writing ...................................................................................................... 11-10
Queue flushing ........................................................................................................................ 11-11
Instruction queue .................................................................................................................... 11-12
Coprocessor data transfer ...................................................................................................... 11-15
Load data buffering ................................................................................................................. 11-17
VIC port timing example ............................................................................................................ 12-5
Interrupt entry sequence ........................................................................................................... 12-7
Typical debug system ............................................................................................................... 13-2
Debug ID Register format ......................................................................................................... 13-6
DTR format ............................................................................................................................. 13-12
Bypass register bit order ........................................................................................................... 14-8
Scan chain 0 bit order ............................................................................................................. 14-11
Scan chain 1 bit order ............................................................................................................. 14-11
Scan chain 4 bit order ............................................................................................................. 14-13
Scan chain 6 bit order ............................................................................................................. 14-17
Scan chain 7 bit order ............................................................................................................. 14-18
ETMCPADDRESS format ......................................................................................................... 15-7
FMAC pipeline .......................................................................................................................... 18-6
DS pipeline ................................................................................................................................ 18-8
LS pipeline ................................................................................................................................ 18-9
Register file access ................................................................................................................... 19-5
Register banks ........................................................................................................................ 19-10
FMDRR instruction format ........................................................................................................ 20-8
FMRRD instruction format ........................................................................................................ 20-9
FMSRR instruction format ....................................................................................................... 20-10
FMRRS instruction format ....................................................................................................... 20-11
ARM DDI 0301H
ID012310
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List of Figures
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