Table 11-5 Retirement Conditions - ARM ARM1176JZF-S Technical Reference Manual

11.6.5 Retirement operations
ARM DDI 0301H
ID012310
Because the tag is changed by the core after each new coprocessor instruction, the tag matches
the first coprocessor instruction following the instruction causing the flush. The coprocessor
must then find the first instruction that has a matching tag, working from the bottom of the
pipeline upwards, and remove all instructions from that point upwards.
Unlike tokens passing down a queue, a flush signal has a fixed delay so that the timing
relationship between a flush in the core and a flush in the coprocessor is known precisely. Most
of the token queues also require flushing and this can also be done using the tags attached to
each instruction. If a match has been found before the stage at the receiving end of a token queue
is passed, then the token queue is cleared.
Otherwise, it must be properly flushed by matching the tags in the queue. This operation must
be performed on all the queues except the finish queue, that is updated in the normal way.
Therefore, the coprocessor must flush the instruction and cancel queues. The flushing operation
can be carried out by the coprocessor as soon as the flush signal is received. The flushing
operation is simplified because the instruction and cancel queues cannot be performing any
other operation. This means that flushing is not required to be combined with queue updates for
these queues.
There is a single cycle following a flush where nothing happens that affects the flushed queues,
and this provides a good opportunity to carry out the queue flushing operation.
The following signals provide the flush broadcast signal from the core:
ACPFLUSH
This signal is asserted when a flush is to be performed.
ACPFLUSHT[3:0]
This is the tag associated with the first instruction to be flushed.
When an instruction reaches the bottom of the coprocessor pipeline it is retired. How it retires
depends on the kind of instruction it is and if it is iterated, as Table 11-5 lists.
Typ
Instruction
e
CDP -
MRC Store
MCR Load
MRRC Store
MCRR Load
STC Store
LDC Load
Table 11-5 lists the conditions for each coprocessor instruction:
• all store instructions retire unconditionally on leaving Ex1 because no token is required in
the finish queue
• CDP instructions require a token in the finish queue
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Retirement conditions
Must find a token in the finish queue.
No conditions. Immediate retirement on leaving Ex1.
All load instructions must find data in the load data pipeline from the core.
No conditions. Immediate retirement on leaving Ex1.
All load instructions must find data in the load data pipeline from the core.
No conditions. Immediate retirement on leaving Ex1.
Must find data in the load data pipeline from the core.
Coprocessor Interface

Table 11-5 Retirement conditions

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