Table 1-13 Operand2; Table 1-14 Fields; Table 1-15 Condition Codes - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
Table 1-13 summarizes Operand2 assembler.
Table 1-14 summarizes the MSR instruction fields.
Suffix Sets this bit in the MSR field_mask
c Control field mask bit, bit 0
x Extension field mask bit, bit 1
s Status field mask bit, bit 2
Flags field mask bit, bit 3
f
Table 1-15 summarizes condition codes.
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Table 1-13 Operand2

Operation Assembler
Immediate value
#<immed_8r>
Logical shift left
<Rm> LSL #<immed_5>
Logical shift right
<Rm> LSR #<immed_5>
Arithmetic shift right
<Rm> ASR #<immed_5>
Rotate right
<Rm> ROR #<immed_5>
Register
<Rm>
Logical shift left
<Rm> LSL <Rs>
Logical shift right <Rm> LSR <Rs>
Arithmetic shift right <Rm> ASR <Rs>
Rotate right <Rm> ROR <Rs>
Rotate right extended <Rm> RRX

Table 1-14 Fields

MSR instruction bit number
16
17
18
19

Table 1-15 Condition codes

Suffix Description
EQ Equal
NE Not equal
Unsigned higher or same, carry set
HS/CS
Unsigned lower, carry clear
LO/CC
Negative, minus
MI
Positive or zero, plus
PL
Overflow
VS
No overflow
VC
Unsigned higher
HI
Introduction
1-43