Table 3-49 Secure Debug Enable Register Bit Functions; Figure 3-30 Secure Debug Enable Register Format - ARM ARM1176JZF-S Technical Reference Manual

3.2.11 c1, Secure Debug Enable Register
ARM DDI 0301H
ID012310
To use the Secure Configuration Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c1
• CRm set to c1
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c1, c1, 0
MCR p15, 0, <Rd>, c1, c1, 0
An attempt to access the Secure Configuration Register from any state other than Secure
privileged results in an Undefined exception.
The purpose of the Secure Debug Enable Register is to provide control of permissions for debug
in Secure User mode, see Chapter 13 Debug.
Table 3-49 lists the purposes of the individual bits in the Secure Debug Enable Register.
The Secure Debug Enable Register is:
• in CP15 c1
• a 32 bit register in the Secure world only
• accessible in Secure privileged modes only.
Figure 3-30 shows the arrangement of bits in the register.
31
Table 3-49 lists how the bit values correspond with the Secure Debug Enable Register functions.
Bits Field name
[31:2] -
[1] SUNIDEN
[0] SUIDEN
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; Read Secure Configuration Register data
; Write Secure Configuration Register data
SBZ

Figure 3-30 Secure Debug Enable Register format

Table 3-49 Secure Debug Enable Register bit functions

Function
This field is UNP when read. Write as the existing value.
Enables Secure User non-invasive debug:
0 = Non-invasive debug is not permitted in Secure User mode, reset value
1 = Non-invasive debug is permitted in Secure User mode.
Enables Secure User invasive debug:
0 = Invasive debug is not permitted in Secure User mode, reset value
1 = Invasive debug is permitted in Secure User mode.
System Control Coprocessor
2 1 0
SUNIDEN
SUIDEN
3-54