Memory Access Sequence - ARM ARM1176JZF-S Technical Reference Manual

6.3

Memory access sequence

6.3.1 TLB match process
ARM DDI 0301H
ID012310
When the processor generates a memory access, the MMU:
1. Performs a lookup for a mapping for the requested virtual address and current ASID and
current world, Secure or Non-secure, in the relevant Instruction or Data MicroTLB.
2. If step 1 misses then a lookup for a mapping for the requested virtual address and current
ASID and current world, Secure or Non-secure, in the main TLB is performed.
If no global mapping, or mapping for the currently selected ASID, or no matching NSTID, for
the virtual address can be found in the TLBs then a translation table walk is automatically
performed by hardware, unless Page Table Walks are disabled by the PD0 or PD1 bits in the
TTB Control register, that cause the processor to return a Section Translation fault. See
Hardware page table translation on page 6-36.
If a matching TLB entry is found then the information it contains is used as follows:
1. The access permission bits and the domain are used to determine if the access is permitted.
If the access is not permitted the MMU signals a memory abort, otherwise the access is
enabled to proceed. Memory access control on page 6-11 describes how this is done.
2. The memory region attributes control the cache and write buffer, and determine if the
access is Secure or Non-secure cached, uncached, or device, and if it is shared, as Memory
region attributes on page 6-14 describes.
3. The physical address is used for any access to external or tightly coupled memory to
perform Tag matching for cache entries.
Each TLB entry contains a virtual address, a page size, a physical address, and a set of memory
properties. Each is marked as being associated with a particular application space, or as global
for all application spaces. Register c13 in CP15 determines the currently selected application
space. This register is duplicated as Secure and Non-secure to enable fast switching between
Secure and Non-secure applications. Each entry is also associated with the Secure or
Non-secure world by the NSTID.
A TLB entry matches if the NSTID matches the Secure or Non-secure request state of the MMU
request, and if bits [31:N] of the Virtual Address match, where N is log
TLB entry. It is either marked as global, or the Application Space IDentifier (ASID) matches the
current ASID. The behavior of a TLB if two or more entries match at any time, including global
and ASID-specific entries, is Unpredictable. The operating system must ensure that, at most,
one TLB entry matches at any time. With respect to operation in the Secure and Non-secure
worlds, multiple matching can only occur on entries with the same NSTID, that is a Non-secure
entry and a Secure entry can never be hit simultaneously.
A TLB can store entries based on the following four block sizes:
Supersections Consist of 16MB blocks of memory.
Sections Consist of 1MB blocks of memory.
Large pages Consist of 64KB blocks of memory.
Small pages Consist of 4KB blocks of memory.
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Memory Management Unit
of the page size for the
2
6-7