Table 3-29 Results Of Access To The Instruction Set Attributes Register 0 - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
Table 3-28 Instruction Set Attributes Register 0 bit functions (continued)
Bits Field name
[19:16] -
[15:12] -
[11:8] -
[7:4] -
[3:0] -
Table 3-29 lists the results of attempted access for each mode.

Table 3-29 Results of access to the Instruction Set Attributes Register 0

Secure Privileged
Read Write
Data Undefined exception
To use the Instruction Set Attributes Register 0 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c2
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c0, c2, 0 ;Read Instruction Set Attributes Register 0
c0, Instruction Set Attributes Register 1
The purpose of the Instruction Set Attributes Register 1 is to provide information about the
instruction set that the processor supports beyond the basic set.
The Instruction Set Attributes Register 1 is:
• in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-22 on page 3-38 shows the bit arrangement for Instruction Set Attributes Register 1.
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Function
Indicates support for coprocessor instructions.
0x4 , ARM1176JZF-S processors support:
• CDP, LDC, MCR, MRC, STC
• CDP2, LDC2, MCR2, MRC2, STC2
• MCRR, MRRC
• MCRR2, MRRC2.
Indicates support for combined compare and branch instructions.
, no support in ARM1176JZF-S processors.
0x0
Indicates support for bitfield instructions.
0x0 , no support in ARM1176JZF-S processors.
Indicates support for bit counting instructions.
, ARM1176JZF-S processors support CLZ.
0x1
Indicates support for atomic load and store instructions.
0x1 , ARM1176JZF-S processors support SWP and SWPB.
Non-secure Privileged
Read Write
Data Undefined exception
System Control Coprocessor
User
Undefined exception
3-37