The Dbgtap Port And Debug Registers; Table 14-1 Supported Public Instructions - ARM ARM1176JZF-S Technical Reference Manual

14.5

The DBGTAP port and debug registers

Binary code
b00000
b00001
b00010
b00011
b00100
b00101
b00110
b00111
b01000
b01001
b01010-b01011
b01100
b01101-b11100
ARM DDI 0301H
ID012310
The processor DBGTAP controller is the part of the debug unit that enables access through the
DBGTAP to the on-chip debug resources, such as breakpoint and watchpoint registers. The
DBGTAP controller is based on the IEEE 1149.1 standard and supports:
• a device ID register
• a bypass register
• a five-bit instruction register
• a five-bit scan chain select register.
In addition, the public instructions that Table 14-1 lists are supported.
Instruction Description
This instruction connects the selected scan chain between DBGTDI and DBGTDO.
EXTEST
When the instruction register is loaded with the EXTEST instruction, the debug scan
chains can be written. See Scan chains on page 14-10.
- Reserved.
Scan_N Selects the Scan Chain Select Register (SCREG). This instruction connects SCREG
between DBGTDI and DBGTDO. See Scan chain select register (SCREG) on
page 14-9.
- Reserved.
Restart Forces the processor to leave Debug state. This instruction is used to exit from Debug
state. The processor restarts when the Run-Test/Idle state is entered.
- Reserved.
- Reserved.
- Reserved.
Halt Forces the processor to enter Debug state. This instruction stops the processor and puts
it into Debug state.
- Reserved.
- Reserved.
This instruction connects the selected scan chain between DBGTDI and DBGTDO.
INTEST
When the instruction register is loaded with the INTEST instruction, the debug scan
chains can be read. See Scan chains on page 14-10.
- Reserved.
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Debug Test Access Port

Table 14-1 Supported public instructions

14-6