ARM ARM1176JZF-S Technical Reference Manual page 561

14.8.8 Reading the CPSR/SPSR
14.8.9 Writing the CPSR/SPSR
ARM DDI 0301H
ID012310
Here R0 is used as a temporary register:
1. Move the contents of CPSR/SPSR to R0.
SCAN_N 5
ITRSEL
INST MRS R0,CPSR
RTI
LOOP
INST 0x00000000 Ready
UNTIL Ready==1
2. Perform the read of R0 using the standard sequence that Reading a current mode ARM
register in the range R0-R14 on page 14-34 describes. Scan chain 5 and ITRsel are already
selected.
Here R0 is used as a temporary register:
1. Load the required value into R0 using the standard sequence that Writing a current mode
ARM register in the range R0-R14 on page 14-34 describes. Now scan chain 5 and
EXTEST are selected.
2. Move the contents of R0 to CPRS/SPRS:
ITRSEL
INST MSR CPSR,R0
RTI
LOOP
INST 0x00000000 Ready
UNTIL Ready==1
This instruction can modify the T and J bits. They have no effect in the execution of instructions
while in Debug state but take effect when the core leaves Debug state.
The CPSR mode and control bits can be written in User mode when the core is in Debug state
and the core is in a Non-secure world or the SPIDEN signal is asserted. This is essential so that
the debugger can change mode and then get at the other banked registers.
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; select DTR
; select the ITR and EXTEST
; or SPSR
; wait until the instruction ends
; select the ITR and EXTEST
; or SPSR
; wait until the instruction ends
Debug Test Access Port
14-35