Table of Contents
Advertisement
Short vector operation
Should Be One (SBO)
Should Be Zero (SBZ)
Should Be Zero or Preserved (SBZP)
Significand
SPSR
Stride
Subnormal value
Support code
Synchronization primitive
Tag
TAP
TCM
Test Access Port (TAP)
Thumb instruction
ARM DDI 0301H
ID012310
A VFP coprocessor operation involving more than one destination register and perhaps more
than one source register in the generation of the result for each destination.
Should be written as 1 (or all 1s for bit fields) by software. Writing a 0 produces Unpredictable
results.
Should be written as 0 (or all 0s for bit fields) by software. Writing a 1 produces Unpredictable
results.
Should be written as 0 (or all 0s for bit fields) by software, or preserved by writing the same
value back that has been previously read from the same field on the same processor.
The component of a binary floating-point number that consists of an explicit or implicit leading
bit to the left of the implied binary point and a fraction field to the right.
See Saved Program Status Register
In the VFP extension, specifies the increment applied to register addresses in short vector
operations. A stride of 00, specifying an increment of +1, causes a short vector operation to
increment each vector register by +1 for each iteration, while a stride of 11 specifies an
increment of +2.
Emin
A value in the range (–2
single-precision and double-precision operands, a subnormal value has a zero exponent and a
nonzero fraction field. The IEEE 754 standard requires that the generation and manipulation of
subnormal operands be performed with the same precision as normal operands.
Software that must be used to complement the hardware to provide compatibility with the
IEEE 754 standard. The support code has a library of routines that performs supported
functions, such as divide with unsupported inputs or inputs that might generate an exception in
addition to operations beyond the scope of the hardware. The support code has a set of exception
handlers to process exceptional conditions in compliance with the IEEE 754 standard.
The memory synchronization primitive instructions are those instructions that are used to ensure
memory synchronization. That is, the LDREX, STREX, SWP, and SWPB instructions.
The upper portion of a block address used to identify a cache line within a cache. The block
address from the CPU is compared with each tag in a set in parallel to determine if the
corresponding line is in the cache. If it is, it is said to be a cache hit and the line can be fetched
from cache. If the block address does not correspond to any of the tags, it is said to be a cache
miss and the line must be fetched from the next level of memory.
See also Cache terminology diagram on the last page of this glossary.
See Test access port.
See Tightly coupled memory.
The collection of four mandatory and one optional terminals that form the input/output and
control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI,
TDO, TMS, and TCK. The optional terminal is TRST. This signal is mandatory in ARM cores
because it is used to reset the debug logic.
A halfword that specifies an operation for an ARM processor in Thumb state to perform. Thumb
instructions must be halfword-aligned.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Emin
< x < 2
), except for 0. In the IEEE 754 standard format for
Glossary
Glossary-17
Hide quick links:
Advertisement
Table of Contents
