Figure 2-2 Memory In The Secure And Non-Secure Worlds - ARM ARM1176JZF-S Technical Reference Manual

Address
Abort
S prot
External
memory
ARM DDI 0301H
ID012310
• in the MMU, Secure and Non-secure descriptors can coexist and they are differentiated
by the NSTID.
In the descriptors the NS attribute indicates whether the corresponding physical memory is
Secure or Non-secure.
For Non-secure descriptors, marked with NSTID=Non-secure, NS attribute is forced to
Non-secure value. The Non-secure world can only target Non-secure memory.
For Secure descriptor, marked with NSTID=Secure, NS attribute indicates if the physical
memory targets Secure or Non-secure memory:
In the caches, instruction and data, each line is tagged as Secure or Non-secure, so that Secure
and Non-secure data can coexist in the cache. Each time a cache line fill is performed, the NS
tag is updated appropriately.
For external accesses, AxPROT[1] indicates whether the access is Secure or Non-secure.
The TrustZone security extensions are completely compatible with existing software. This
means that existing applications and operating systems access memory without change. Where
a system employs Secure functionality the Non-secure world is effectively blind to Secure
memory. This means that Secure and Non-secure memory can co-exist with no affect on
Non-secure code.
Figure 2-2 shows the basic connection of the Secure and Non-secure memory.
Core
Core world
Abort
state
MMU
NSTID
NS attribute
Descriptor 1 S S
Descriptor 2 NS NS
Descriptor (n-1) NS NS
Descriptor (n) NS S
Page
table
walk
Abort
Address
Control
Data
AxPROT[1] Abort
S prot
Secure
slave
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Cache
Line 1 S
Line 2 NS
Line(n-1) NS
Line (n) S
Data
AXI interface
AxPROT[1]
AxPROT[1]
Non-
secure
slave

Figure 2-2 Memory in the Secure and Non-secure worlds

Programmer's Model
Data
TCM
Line 1
Line 2
Line(n-1)
Line(n)
NS access bit
Data
Arbiter Decoder
Master
peripheral
2-6