Table 3-1 System Control Coprocessor Register Functions - ARM ARM1176JZF-S Technical Reference Manual

Function
System control
and configuration
MMU control and
configuration
ARM DDI 0301H
ID012310
Table 3-2 on page 3-14 lists the registers in the system control processor in register order and
gives their reset values.
Register/operation
Control
Auxiliary control
Secure Configuration
Secure Debug Enable
Non-Secure Access Control
Coprocessor Access Control
Secure or Non-secure Vector Base
Address
Monitor Vector Base Address
a
ID code
Feature ID, CPUID scheme
TLB Type
Translation Table Base 0
Translation Table Base 1
Translation Table Base Control
Domain Access Control
Data Fault Status
Instruction Fault Status
Fault Address
Instruction Fault Address
Watchpoint Fault Address
TLB Operations
TLB Lockdown
Memory Region Remap
Peripheral Port Memory Remap
Context ID
FCSE PID
Thread And Process ID
TLB Lockdown Access
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Table 3-1 System control coprocessor register functions

Reference to description
c1, Control Register on page 3-44
c1, Auxiliary Control Register on page 3-48
c1, Secure Configuration Register on page 3-52
c1, Secure Debug Enable Register on page 3-54
c1, Non-Secure Access Control Register on page 3-55
c1, Coprocessor Access Control Register on page 3-51
c12, Secure or Non-secure Vector Base Address Register on
page 3-121
c12, Monitor Vector Base Address Register on page 3-122
c0, Main ID Register on page 3-20
c0, CPUID registers on page 3-26
c0, TLB Type Register on page 3-25
c2, Translation Table Base Register 0 on page 3-57
c2, Translation Table Base Register 1 on page 3-59
c2, Translation Table Base Control Register on page 3-60
c3, Domain Access Control Register on page 3-63
c5, Data Fault Status Register on page 3-64
c5, Instruction Fault Status Register on page 3-66
c6, Fault Address Register on page 3-68
c6, Instruction Fault Address Register on page 3-69
c6, Watchpoint Fault Address Register on page 3-69
c8, TLB Operations Register on page 3-86
c10, TLB Lockdown Register on page 3-100
c10, Memory region remap registers on page 3-101
c15, Peripheral Port Memory Remap Register on
page 3-130
c13, Context ID Register on page 3-128
c13, FCSE PID Register on page 3-126
c13, Thread and process ID registers on page 3-129
c15, TLB lockdown access registers on page 3-149
System Control Coprocessor
3-3