Figure - ARM ARM1176JZF-S Technical Reference Manual

Front of queue pointer
Fully-associative cache
Halfword
Halting debug-mode
High vectors
Hit-Under-Miss (HUM)
Host
HUM
IEM
Illegal instruction
IMB
Implementation-defined
Implementation-specific
Imprecise tracing
Index
Index register
Infinity
ARM DDI 0301H
ID012310
Pointer to the next entry to be written to in the write buffer.
A cache that has only one cache set that consists of the entire cache. The number of cache entries
is the same as the number of cache ways.
See also Direct-mapped cache.
A 16-bit data item.
One of two mutually exclusive debug modes. In Halting debug-mode all processor execution
halts when a breakpoint or watchpoint is encountered. All processor state, coprocessor state,
memory and input/output locations can be examined and altered by the JTAG interface.
See also Monitor debug-mode.
Alternative locations for exception vectors. The high vector address range is near the top of the
address space, rather than at the bottom.
A buffer that enables program execution to continue, even though there has been a data miss in
the cache.
A computer that provides data and other services to another computer. Especially, a computer
providing debugging services to a target being debugged.
See Hit-Under-Miss.
See Intelligent Energy Management.
An instruction that is architecturally Undefined.
See Instruction Memory Barrier.
Means that the behavior is not architecturally defined, but should be defined and documented
by individual implementations.
Means that the behavior is not architecturally defined, and does not have to be documented by
individual implementations. Used when there are a number of implementation options available
and the option chosen does not affect software compatibility.
A filtering configuration where instruction or data tracing can start or finish earlier or later than
expected. Most cases cause tracing to start or finish later than expected.
For example, if TraceEnable is configured to use a counter so that tracing begins after the fourth
write to a location in memory, the instruction that caused the fourth write is not traced, although
subsequent instructions are. This is because the use of a counter in the TraceEnable
configuration always results in imprecise tracing.
See Cache index.
A register specified in some load or store instructions. The value of this register is used as an
offset to be added to or subtracted from the base register value to form the virtual address, which
is sent to memory. Some addressing modes optionally enable the index register value to be
shifted prior to the addition or subtraction.
In the IEEE 754 standard format to represent infinity, the exponent is the maximum for the
precision and the fraction is all zeros.
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