Sign In
Upload
Manuals
Brands
ARM Manuals
Computer Hardware
ARM946E-S
ARM ARM946E-S Manuals
Manuals and User Guides for ARM ARM946E-S. We have
1
ARM ARM946E-S manual available for free PDF download: Technical Reference Manual
ARM ARM946E-S Technical Reference Manual (189 pages)
Brand:
ARM
| Category:
Computer Hardware
| Size: 1 MB
Table of Contents
Table of Contents
3
Copyright © ARM Limited 2000. All Rights Reserved. ARM DDI
6
Preface
11
About this Document
12
Further Reading
15
Feedback
16
Chapter 1 Introduction
17
About the ARM946E-S
18
Microprocessor Block Diagram
19
Figure 1-1 ARM946E-S Block Diagram
19
Chapter 2 Programmer's Model
20
Table 1-1 Location of Block Descriptions
20
About the ARM94E-S Programmer's Model
22
About the ARM9E-S Programmer's Model
23
CP15 Register Map Summary
24
Table 2-1 CP15 Register Map
24
Table 2-2 CP15 Abbreviations
25
Figure 2-1 CP15 MRC and MCR Bit Pattern
26
Table 2-3 Register 0, ID Code
27
Table 2-4 Cache Type Register Format
27
Table 2-5 Cache Size Encoding
28
Table 2-6 Cache Associativity Encoding
29
Table 2-7 Tightly-Coupled Memory Size Register
30
Table 2-8 Memory Size Field
30
Table 2-9 Register 1, Control Register
31
Table 2-10 Programming Instruction/Data Cachable Bits
35
Table 2-11 Programming Data Bufferable Bits
36
Table 2-12 Programming Instruction and Data Access Permission Bits (Extended)
37
Table 2-13 Access Permission Encoding (Extended)
37
Table 2-14 Instruction and Data Access Permission Bits (Standard)
38
Table 2-15 Access Permission Encoding (Standard)
39
Table 2-16 Accessing Protection Region/Base Size Registers
40
Table 2-17 Protection Region/Base Size Register Format
40
Table 2-18 Area Size Encoding
41
Table 2-19 Cache Operations
42
Table 2-20 Index Fields for Supported Cache Sizes
43
Figure 2-2 Index and Segment Format
43
Figure 2-3 Icache Address Format
44
Table 2-21 Lockdown Register Format
45
Table 2-22 Protection Region/Base Size Register Format
46
Table 2-23 Tightly-Coupled Memory Area Size Encoding
47
Table 2-24 Register 15, bist Instructions
49
Table 2-25 Register 15, Implementation-Specific bist Instructions
49
Figure 2-4 Process ID Format
49
Table 2-26 Test State Register Bit Assignments
50
Table 2-27 Additional Operations
51
Figure 2-5 Index/Segment Format
52
Figure 2-6 Data Format TAG Read/Write Operations
52
Table 2-28 Index Fields for Supported Cache Sizes
53
Chapter 3 Caches
56
Cache Architecture
56
Figure 3-1 Example 8K Cache
57
Table 3-1 TAG and Index Fields for Supported Cache Sizes
58
Figure 3-2 Access Address for a 4KB Cache
59
Icache
60
Dcache
62
Table 3-2 Meaning of CD Bit Values
63
Figure 3-3 Register 7, Rd Format
64
Table 3-3 Calculating Index Addresses
65
Cache Lockdown
66
Chapter 4 Protection Unit
72
About the Protection Unit
72
Figure 4-1 ARM946E-S Protection Unit
72
Memory Regions
73
Table 4-1 Protection Register Format
73
Table 4-2 Region Size Encoding
74
Overlapping Regions
76
Figure 4-2 Overlapping Memory Regions
76
Chapter 5 Tightly-Coupled SRAM
79
ARM946E-S SRAM Requirements
80
Figure 5-1 SRAM Read Cycle
80
Using CP15 Control Register
81
Chapter 6 Bus Interface Unit and Write Buffer
86
About the BIU and Write Buffer
86
AHB Bus Master Interface
87
Table 6-1 Supported Burst Types
88
Figure 6-1 Linefetch Transfer
88
Figure 6-2 Back to Back Linefetches
89
Figure 6-3 Nonsequential Uncached Accesses
90
Figure 6-4 Data Burst Followed by Instruction Fetch
90
Figure 6-5 Crossing a 1KB Boundary
91
Noncached Thumb Instruction Fetches
92
AHB Clocking
93
Figure 6-6 AHB Clock Relationships
94
Figure 6-7 ARM946E-S CLK to AHB HCLK Sampling
95
The Write Buffer
96
Table 6-2 Data Write Modes
96
Chapter 7 Coprocessor Interface
100
About the Coprocessor Interface
100
Figure 7-1 Coprocessor Clocking
100
Ldc/Stc
102
Figure 7-2 LDC/STC Cycle Timing
102
Table 7-1 Handshake Encoding
105
Mcr/Mrc
106
Figure 7-3 MCR/MRC Transfer Timing with Busy-Wait
106
Interlocked MCR
108
Figure 7-4 Interlocked MCR/MRC Timing with Busy-Wait
108
Cdp
109
Figure 7-5 Late Cancelled CDP
109
Privileged Instructions
110
Figure 7-6 Privileged Instructions
110
Busy-Waiting and Interrupts
111
Figure 7-7 Busy-Waiting and Interrupts
111
Chapter 8 Debug Support
114
About the Debug Interface
114
Figure 8-1 Clock Synchronization
115
Debug Systems
116
Figure 8-2 Typical Debug System
116
Figure 8-3 ARM9E-S Block Diagram
118
The JTAG State Machine
119
Figure 8-4 Test Access Port (TAP) Controller State Transitions
119
Table 8-1 Public Instructions
121
Scan Chains
124
Table 8-2 ARM946E-S Scan Chain Allocations
124
Table 8-3 Scan Chain 1 Bits
125
Table 8-4 Scan Chain 15 Addressing Mode Bit Order
126
Table 8-5 Mapping of Scan Chain 15 Address Field to CP15 Registers
126
Debug Access to the Caches
129
Figure 8-5 TAG Address Format
129
Figure 8-6 Cache Index Register Format
130
Debug Interface Signals
131
Figure 8-7 Breakpoint Timing
131
Figure 8-8 Watchpoint Entry with Data Processing Instruction
133
Figure 8-9 Watchpoint Entry with Branch
134
ARM9E-S Core Clock Domains
136
Determining the Core and System State
137
Overview of Embeddedice-RT
138
Figure 8-10 the ARM9E-S, TAP Controller, and Embeddedice-RT
138
8.10 Disabling Embeddedice-RT
140
8.11 the Debug Communications Channel
141
Table 8-6 Coprocessor 14 Register Map
141
Figure 8-11 Debug Comms Channel Status Register
142
Figure 8-12 Coprocessor 14 Debug Status Register Format
143
8.12 Real-Time Debug
145
Chapter 9 ETM Interface
147
About the ETM Interface
148
Figure 9-1 ARM946E-S ETM Interface
149
Enabling the ETM Interface
150
Chapter 10 Test Support
152
10.1 about the ARM946E-S Test Methodology
152
10.2 Scan Insertion and ATPG
153
10.3 bist of Memory Arrays
155
Table 10-1 Instruction bist Address and General Registers
157
Table 10-2 Data bist Address and General Registers
157
Appendix Aac Parameters
159
Timing Diagrams
159
Figure A-1 Clock, Reset, and AHB Enable Timing
160
Figure A-2 AHB Bus Request and Grant Related Timing
160
A.1 Timing Diagrams
160
Figure A-3 AHB Bus Master Timing
161
Figure A-4 Coprocessor Interface Timing
162
Figure A-5 Debug Interface Timing
163
Figure A-6 JTAG Interface Timing
164
Figure A-7 DBGSDOUT to DBGTDO Timing
164
Figure A-8 Exception and Configuration Timing
165
Figure A-9 INTEST Wrapper Timing
165
Figure A-10 ETM Interface Timing
166
AC Timing Parameter Definitions
167
Table A-1 Timing Parameter Definitions
167
Appendix B Signal Descriptions
173
Signal Properties and Requirements
174
Clock Interface Signals
175
Table B-1 Clock Interface Signals
175
AHB Signals
176
Table B-2 AHB Signals
176
B.3 AHB Signals
176
Coprocessor Interface Signals
178
Table B-3 Coprocessor Interface Signals
178
Debug Signals
180
Table B-4 Debug Signals
180
B.5 Debug Signals
180
JTAG Signals
182
Table B-5 JTAG Signals
182
B.6 JTAG Signals
182
Miscellaneous Signals
183
Table B-6 Miscellaneous Signals
183
B.7 Miscellaneous Signals
183
ETM Interface Signals
184
Table B-7 ETM Interface Signals
184
INTEST Wrapper Signals
186
Table B-8 INTEST Wrapper Signals
186
Advertisement
Advertisement
Related Products
ARM ARM926EJ-S
ARM ARM9TDMI
ARM ARM966E-S
ARM ARM1176JZF-S
ARM ARM7TDMI
ARM Cortex A9
ARM ARM710T
ARM ARM1136JF-S
ARM ARM11
ARM Cordio BT4 Radio IP
ARM Categories
Computer Hardware
Motherboard
Controller
Processor
Computer Accessories
More ARM Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL