Table 3-16 Debug Feature Register 0 Bit Functions; Figure 3-16 Debug Feature Register 0 Format; Table 3-17 Results Of Access To The Debug Feature Register 0 - ARM ARM1176JZF-S Technical Reference Manual

Bits Field name
[31:28] -
[27:24] -
[23:20] -
[19:16] -
[15:12] -
[11:8] -
[7:4] -
[3:0] -
ARM DDI 0301H
ID012310
c0, Debug Feature Register 0
The purpose of the Debug Feature Register 0 is to provide information about the debug system
for the processor.
Debug Feature Register 0 is:
• in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-16 shows the bit arrangement for Debug Feature Register 0.
31 28 27 24 23
Reserved Reserved
Table 3-16 lists how the bit values correspond with the Debug Feature Register 0 functions.
Function
Reserved. RAZ.
Reserved. RAZ.
Indicates the type of memory-mapped microcontroller debug model that the processor
supports.
, ARM1176JZF-S processors do not support this debug model.
0x0
Indicates the type of memory-mapped Trace debug model that the processor supports.
0x0 , ARM1176JZF-S processors do not support this debug model.
Indicates the type of coprocessor-based Trace debug model that the processor supports.
, ARM1176JZF-S processors do not support this debug model.
0x0
Indicates the type of embedded processor debug model that the processor supports.
, ARM1176JZF-S processors do not support this debug model.
0x0
Indicates the type of Secure debug model that the processor supports.
, ARM1176JZF-S processors support the v6.1 Secure debug architecture based model.
0x3
Indicates the type of applications processor debug model that the processor supports.
, ARM1176JZF-S processors support the v6.1 debug model.
0x3
Table 3-17 lists the results of attempted access for each mode.
Secure Privileged
Read Write
Data Undefined exception
To use the Debug Feature Register 0 read CP15 with:
• Opcode_1 set to 0
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
20 19 16 15
- - -

Figure 3-16 Debug Feature Register 0 format

Table 3-16 Debug Feature Register 0 bit functions

Table 3-17 Results of access to the Debug Feature Register 0

Non-secure Privileged
Read Write
Data Undefined exception
System Control Coprocessor
12 11 8 7 4 3
- -
User
Undefined exception
0
-
3-29