Table 3-123 Monitor Vector Base Address Register Bit Functions; Table 3-124 Results Of Access To The Monitor Vector Base Address Register - ARM ARM1176JZF-S Technical Reference Manual

Bits Field name
[31:5] Monitor vector base
address
[4:0] SBZ
3.2.45 c12, Interrupt Status Register
ARM DDI 0301H
ID012310
Table 3-123 lists how the bit values correspond with the Monitor Vector Base Address Register
functions.
Function
Determines the location that the core branches to on a Secure Monitor mode exception.
Holds the base address. The reset value is 0.
UNP/SBZ.
When an exception branches to the Secure Monitor mode, the core branches to address:
Monitor_Base_Address + Exception_Vector_Address.
The Secure Monitor Call Exception caused by an SMC instruction branches to Secure Monitor
mode. You can configure IRQ, FIQ, and External abort exceptions to branch to Secure Monitor
mode, see c1, Secure Configuration Register on page 3-52. These are the only exceptions that
can branch to Secure Monitor mode and that use the Monitor Vector Base Address Register to
calculate the branch address. For more information about exceptions, see Exception vectors on
page 2-48.
Note
The Monitor Vector Base Address Register is
program the register with an appropriate value for the Secure Monitor.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Table 3-124 lists the results of attempted access for each mode.

Table 3-124 Results of access to the Monitor Vector Base Address Register

Secure Privileged
Read
Data
To use the Monitor Vector Base Address Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c12
• CRm set to c0
• Opcode_2 set to 1.
For example:
MRC p15, 0, <Rd>, c12, c0, 1
MCR p15, 0, <Rd>, c12, c0, 1
The purpose of the Interrupt Status Register is to:
reflect the state of the nFIQ and nIRQ pins on the processor
•
• to reflect the state of external aborts.
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Table 3-123 Monitor Vector Base Address Register bit functions

0x00000000
Non-secure Privileged
Write
Data Undefined exception
; Read Monitor Vector Base Address Register
; Write Monitor Vector Base Address Register
System Control Coprocessor
at reset. The Secure boot code must
User
Undefined exception
3-123