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MRC p15, 3, <Rd>, c15, c8, <Register Number>
MCR p15, 3, <Rd>, c15, c8, <Register Number>
3.2.59
c15, Data Cache Master Valid Register
MRC p15, 3, <Rd>, c15, c12, <Register Number>
MCR p15, 3, <Rd>, c15, c12, <Register Number>
ARM DDI 0301H
ID012310
Attempts to access the register in modes other than Secure privileged result in an Undefined
exception.
To use the Instruction Cache Master Valid Register write CP15 with:
•
Opcode_1 set to 3
•
CRn set to c15
•
CRm set to c8
•
Opcode_2 set to <Register Number>.
The <Register Number> field of the instruction designates one of the registers required to
capture all the Valid bits. The highest Register Number is one less than the number of times 8KB
divides into the cache size.
The purpose of the Data Cache Master Valid Register is to save and restore the Data cache
master valid bits on entry to and exit from dormant mode, see Dormant mode on page 10-4. You
might also use this register during debug.
The Data Cache Master Valid Register is:
•
in CP15 c15
•
a 32-bit read/write register in the Secure world only
•
accessible in privileged modes only.
The number of Master Valid bits in the register is a function of the cache size. There is one
Master Valid bit for each 8 cache lines:
For instance, there are 64 Master Valid bits for a 16KB cache. You can access Master Valid bits
through 32-bit registers indexed using Opcode_2. The maximum number of 32-bit registers
required for the largest cache size, 64KB, is 8. The Master Valid bits fill the registers from the
LSB of the lowest numbered register upwards.
Writes to unimplemented Valid bits have no effect, and reads return 0. The reset value is 0.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Attempts to access the register in modes other than Secure privileged result in an Undefined
exception.
To use the Data Cache Master Valid Register write CP15 with:
•
Opcode_1 set to 3
•
CRn set to c15
•
CRm set to c12
•
Opcode_2 set to <Register Number>.
The <Register Number> field of the instruction designates one of the registers required to
capture all the Valid bits. The highest Register Number is one less than the number of times 8KB
divides into the cache size.
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; Read Instruction Cache Master Valid Register
; Write Instruction Cache Master Valid Register
Master Valid bits =
; Read Data Cache Master Valid Register
; Write Data Cache Master Valid Register
System Control Coprocessor
cache size
line length in bytes x 8
3-148
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