ARM Cortex-A76 Core Technical Reference Manual

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Arm

Cortex

-A76 Core

Revision: r3p0

Technical Reference Manual

100798_0300_00_en

Table of Contents

Summary of Contents for ARM Cortex-A76 Core

Page 2 Use of the word “partner” in reference to Arm’s customers is not intended to create or refer to any partnership relationship with any other company.
Page 3 This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.
Page 5: Table Of Contents
About the Generic Timer ..................A2-40 Chapter A3 Clocks, resets, and input synchronization A3.1 About clocks, resets, and input synchronization ..........A3-42 A3.2 Asynchronous interface ..................A3-43 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 6 Bypassing the CPU interface ................A9-113 Chapter A10 Advanced SIMD and floating-point support A10.1 About the Advanced SIMD and floating-point support ........A10-116 A10.2 Accessing the feature identification registers ............ A10-117 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 7 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1 ..B2-201 B2.42 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1 ..B2-202 B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1 ........................B2-203 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 8 B2.90 SCTLR_EL1, System Control Register, EL1 ............B2-273 B2.91 SCTLR_EL2, System Control Register, EL2 ............B2-275 B2.92 SCTLR_EL3, System Control Register, EL3 ............B2-276 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 9 ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1 ....B4-333 B4.18 AArch64 virtual interface control system register summary ........ B4-335 B4.19 ICH_AP0R0_EL2, Interrupt Controller Hyp Active Priorities Group 0 Register 0, EL2 ..........................B4-336 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 10 ETM trace unit register interfaces ..............C4-398 C4.7 Interaction with the PMU and Debug ..............C4-399 Part D Debug registers Chapter D1 AArch32 debug registers D1.1 AArch32 debug register summary ..............D1-404 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 11 PMPIDR3, Performance Monitors Peripheral Identification Register 3 ....D6-468 D6.11 PMPIDR4, Performance Monitors Peripheral Identification Register 4 ....D6-469 D6.12 PMPIDRn, Performance Monitors Peripheral Identification Register 5-7 ..D6-470 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 12 TRCEVENTCTL0R, Event Control 0 Register ............ D9-530 D9.27 TRCEVENTCTL1R, Event Control 1 Register ............ D9-532 D9.28 TRCEXTINSELR, External Input Select Register ..........D9-533 D9.29 TRCIDR0, ID Register 0 ..................D9-534 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 13 TRCVISSCTLR, ViewInst Start-Stop Control Register ........D9-586 D9.75 TRCVMIDCVR0, VMID Comparator Value Register 0 ........D9-587 D9.76 TRCVMIDCCTLR0, Virtual context identifier Comparator Control Register 0 . . D9-588 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 14 Load/Store accesses crossing page boundaries ........Appx-A-593 Armv8 Debug UNPREDICTABLE behaviors ..........Appx-A-594 Other UNPREDICTABLE behaviors ............Appx-A-597 Appendix B Revisions Revisions ....................Appx-B-600 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 15: Preface
This preface introduces the Arm Cortex -A76 Core Technical Reference Manual. ® ® It contains the following: • About this book on page • Feedback on page 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 16: About This Book
This chapter describes the clocks, resets, and input synchronization of the Cortex-A76 core. Chapter A4 Power management This chapter describes the power domains and the power modes in the Cortex-A76 core. Chapter A5 Memory Management Unit This chapter describes the Memory Management Unit (MMU) of the Cortex-A76 core.
Page 17 Part C Debug descriptions This part describes the debug functionality of the Cortex-A76 core. Chapter C1 Debug This chapter describes the Cortex-A76 core debug registers and shows examples of how to use them. Chapter C2 Performance Monitor Unit This chapter describes the Performance Monitor Unit (PMU) and the registers that it uses.
Page 18 Glossary is a list of terms used in Arm documentation, together with definitions for those ® terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning. See the Glossary for more information.
Page 19 Low Power Interface Specification Arm Q-Channel and P-Channel Interfaces (IHI ® ® 0068). • Reliability, Availability, and Serviceability (RAS) Specification, Armv8, for the Armv8- ® A architecture profile (DDI 0587A). 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 20 Other publications • ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic. Note Arm floating-point terminology is largely based on the earlier ANSI/IEEE Std 754-1985 issue of the standard. See the Arm Architecture Reference Manual Armv8, for Armv8-A ® architecture profile for more information.
Page 21: Feedback
A concise explanation of your comments. Arm also welcomes general suggestions for additions and improvements. Note Arm tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader. 100798_0300_00_en Copyright ©...
Page 23: Part A Functional Description
Part A Functional description...
Page 25: Chapter A1
Chapter A1 Introduction This chapter provides an overview of the Cortex-A76 core and its features. It contains the following sections: • A1.1 About the core on page A1-26. • A1.2 Features on page A1-27. • A1.3 Implementation options on page A1-28.
Page 26: A1.1 About The Core
The PSTATE Speculative Store Bypass Safe (SSBS) bit and the speculation barriers (CSDB, SSBB, PSSBB) instructions introduced in the Armv8.5-A extension. The Cortex-A76 core has a Level 1 (L1) memory system and a private, integrated Level 2 (L2) cache. It also includes a superscalar, variable-length, out-of-order pipeline.
Page 27: A1.2 Features
Activity Monitor Unit (AMU). • Optional Coresight Embedded Logic Analyzer (ELA). See the Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile for more ® information. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A1-27 reserved. Non-Confidential...
Page 28: A1.3 Implementation Options
See the Arm CoreSight ELA-500 The default and recommended value for ® ™ Embedded Logic Analyzer Technical Cortex-A76 is 6. Reference Manual for the full supported range. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A1-28 reserved. Non-Confidential...
Page 29: Supported Standards And Specifications
A1 Introduction A1.4 Supported standards and specifications A1.4 Supported standards and specifications The Cortex-A76 core implements the Armv8-A architecture and some architecture extensions. It also supports interconnect, interrupt, timer, debug, and trace architectures. Table A1-2 Compliance with standards and specifications Architecture...
Page 30: A1.5 Test Features
A1.5 Test features A1.5 Test features The Cortex-A76 core provides test signals that enable the use of both Automatic Test Pattern Generation (ATPG) and Memory Built-In Self Test (MBIST) to test the core logic and memory arrays. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A1-30 reserved.
Page 31: A1.6 Design Tasks
The Cortex-A76 core is delivered as a synthesizable Register Transfer Level (RTL) description in Verilog HDL. Before you can use the Cortex-A76 core, you must implement it, integrate it, and program it. A different party can perform each of the following tasks. Each task can include implementation and integration choices that affect the behavior and features of the core.
Page 32: A1.7 Product Revisions
Implemented new barriers PSSBB and CSDB. Support for Speculative Store Bypass Safe (SSBS) bit enabling software to indicate whether hardware is permitted to load or store speculatively. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A1-32 reserved. Non-Confidential...
Page 33: Chapter A2
Chapter A2 Technical overview This chapter describes the structure of the Cortex-A76 core. It contains the following sections: • A2.1 Components on page A2-34. • A2.2 Interfaces on page A2-38. • A2.3 About system control on page A2-39. • A2.4 About the Generic Timer on page A2-40.
Page 34: A2.1 Components
The main components of the Cortex-A76 core are: • Instruction fetch. • Instruction decode. • Register rename. • Instruction issue. • Execution pipelines. • L1 data memory system. • L2 memory system. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A2-34 reserved. Non-Confidential...
Page 35 A2 Technical overview A2.1 Components The following figure is an overview of the Cortex-A76 core. DynamIQ™ Cluster Core 3* Core 2* Core 1* Core 0 Register Rename Execution Pipeline Instruction Issue/Commit Instruction Click and type. Right-click to select fill color.
Page 36 There are multiple asynchronous bridges between the Cortex-A76 core and the DSU. Only the CPU bridge between the Cortex-A76 core and the DSU can be configured to run synchronously, however it does not affect the other interfaces such as debug, trace, and GIC which are always asynchronous. For...
Page 37 Chapter A9 Generic Interrupt Controller CPU interface on page A9-111 Chapter C1 Debug on page C1-365 Chapter C2 Performance Monitor Unit on page C2-371 Chapter C4 Embedded Trace Macrocell on page C4-391 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A2-37 reserved. Non-Confidential...
Page 38: A2.2 Interfaces
A2 Technical overview A2.2 Interfaces A2.2 Interfaces The Cortex-A76 core has several interfaces to connect it to a SoC. The DSU manages all interfaces. For information on the interfaces, see the Arm DynamIQ Shared Unit Technical Reference Manual. ® ™...
Page 39: A2.3 About System Control
The system registers are accessible in the AArch64 EL0-EL3 and AArch32 EL0 Execution state. Some of the system registers are accessible through the external debug interface. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A2-39 reserved. Non-Confidential...
Page 40: A2.4 About The Generic Timer
• A Hypervisor virtual timer. The Cortex-A76 core does not include the system counter. This resides in the SoC. The system counter value is distributed to the core with a 64-bit bus. For more information on the Generic Timer, see the Arm...
Page 41: Chapter A3
Chapter A3 Clocks, resets, and input synchronization This chapter describes the clocks, resets, and input synchronization of the Cortex-A76 core. It contains the following sections: • A3.1 About clocks, resets, and input synchronization on page A3-42. • A3.2 Asynchronous interface on page A3-43.
Page 42: About Clocks, Resets, And Input Synchronization
About clocks, resets, and input synchronization The Cortex-A76 core supports hierarchical clock gating. The Cortex-A76 core contains several interfaces that connect to other components in the system. These interfaces can be in the same clock domain or in other clock domains.
Page 43: A3.2 Asynchronous Interface
Your implementation can include an optional asynchronous interface between the core and the DSU top level. See the Arm DynamIQ Shared Unit Technical Reference Manual for more information. ® ™ 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A3-43 reserved. Non-Confidential...
Page 45: Chapter A4
Chapter A4 Power management This chapter describes the power domains and the power modes in the Cortex-A76 core. It contains the following sections: • A4.1 About power management on page A4-46. • A4.2 Voltage domains on page A4-47. • A4.3 Power domains on page A4-48.
Page 46: A4.1 About Power Management
A4 Power management A4.1 About power management A4.1 About power management The Cortex-A76 core provides mechanisms to control both dynamic and static power dissipation. Dynamic power management includes the following features: • Architectural clock gating. • Per-core Dynamic Voltage and Frequency Scaling (DVFS).
Page 47: A4.2 Voltage Domains
The Cortex-A76 core supports a VCPU voltage domain and a VSYS voltage domain. The following figure shows the VCPU and VSYS voltage domains in each Cortex-A76 core and in the DSU. The example shows a configuration with four Cortex-A76 cores.
Page 48: A4.3 Power Domains
A4.3 Power domains A4.3 Power domains The Cortex-A76 core contains a core power domain (PDCPU), and a core top-level SYS power domain (PDSYS) where all the Cortex-A76 core I/O signals go through. The PDCPU power domain contains all logic and part of the core asynchronous bridge that enyo_cpu belongs to the VCPU domain.
Page 49 PDSYS VSYS voltage domain Figure A4-2 Cortex-A76 core power domain diagram at enyo_core level The following figure shows the power domains in the DSU, where everything in the same color is part of the same power domain. The example shows four Cortex-A76 cores. The number of Cortex-A76 cores can vary, and the number of domains increases based on the number of Cortex-A76 cores present.
Page 50: A4.4 Architectural Clock Gating Modes
A4.4 Architectural clock gating modes When the Cortex-A76 core is in standby mode, it is architecturally clock gated at the top of the clock tree. Wait for Interrupt (WFI) and Wait for Event (WFE) are features of Armv8-A architecture that put the core in a low-power standby mode by architecturally disabling the clock at the top of the clock tree.
Page 51 The EVENTI input signal is asserted. • The core detects a reset. For more information, see the Arm Architecture Reference Manual Armv8, for Armv8-A architecture ® profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A4-51 reserved. Non-Confidential...
Page 52: A4.5 Power Control
All power mode transitions are performed at the request of the power controller, using a P-Channel interface to communicate with the Cortex-A76 core. There is one P-Channel per core, plus one P-Channel for the cluster. The Cortex-A76 core provides the current requirements on the PACTIVE signals, so that the power controller can make decisions and request any change with PREQ and PSTATE.
Page 53: A4.6 Core Power Modes
RAM within the core domain. A4.6.2 The Cortex-A76 core supports a full shutdown mode where power can be removed completely and no state is retained. The shutdown can be for either the whole cluster or just for an individual core, which allows other cores in the cluster to continue operating.
Page 56: A4.7 Encoding For Power Modes
It is tied off to 0 and should be inferred when all other PACTIVE bits are LOW. For more information, see the AMBA Low Power Interface Specification Arm ® ® Channel and P-Channel Interfaces. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A4-56 reserved. Non-Confidential...
Page 57: A4.8 Power Domain States For Power Modes
However, only some powered-up and powered-down domain combinations are valid and supported. The following information shows the supported power domain states for the Cortex-A76 core. The PDCPU power domain supports the power states described in the following table.
Page 58: A4.9 Power Up And Down Sequences
Core powerup To bring a core into coherence after reset, no software steps are required. Related references B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1 on page B2-188 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A4-58 reserved. Non-Confidential...
Page 59: A4.10 Debug Over Powerdown
A4.10 Debug over powerdown The Cortex-A76 core supports debug over powerdown, which allows a debugger to retain its connection with the core even when powered down. This enables debug to continue through powerdown scenarios, rather than having to re-establish a connection each time the core is powered up.
Page 61: Chapter A5
Chapter A5 Memory Management Unit This chapter describes the Memory Management Unit (MMU) of the Cortex-A76 core. It contains the following sections: • A5.1 About the MMU on page A5-62. • A5.2 TLB organization on page A5-64. • A5.3 TLB match process on page A5-65.
Page 62: A5.1 About The Mmu
The TLB entries contain a Virtual Machine Identifier (VMID) to permit virtual machine switches by the hypervisor without requiring the TLB to be invalidated. A5.1.2 AArch64 behavior The Cortex-A76 core is an Armv8 compliant core that supports execution in AArch64 state. The following table shows the AArch64 behavior. Table A5-2 AArch64 behavior AArch64...
Page 63 A5 Memory Management Unit A5.1 About the MMU The Cortex-A76 core also supports the Virtualization Host Extension (VHE) including ASID space for EL2. When VHE is implemented and enabled, EL2 has the same behavior as EL1. See the Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile for more ®...
Page 64: A5.2 Tlb Organization
The main TLB is invalidated automatically at reset unless the DISCACHEINVLD signal is set HIGH when the Cortex-A76 core is reset. This signal must only be used in diagnostic mode. If caches are not invalidated on reset, their functionality cannot be guaranteed. See the Arm...
Page 65: A5.3 Tlb Match Process
— EL2 in Non-secure state with HCR_EL2.E2H and HCR_EL2.TGE set to 1. — EL1 or EL0 in Secure state. — EL1 or EL0 in Non-secure state. VMID is relevant for EL1 or EL0 in Non-secure state. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A5-65 reserved. Non-Confidential...
Page 66: A5.4 Translation Table Walks
A5.4 Translation table walks A5.4 Translation table walks When the Cortex-A76 core generates a memory access, the MMU: 1. Performs a lookup for the requested VA, current ASID, current VMID, and current translation regime in the relevant instruction or data.
Page 67: A5.5 Mmu Memory Accesses
Write-Back, then the core returns an abort with the following encoding: • ESR.ELx.DFSC = for Data Aborts in AArch64. 0b110001 • ESR.ELx.IFSC = for Instruction Aborts in AArch64. 0b110001 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A5-67 reserved. Non-Confidential...
Page 68: A5.6 Specific Behaviors On Aborts And Memory Attributes
Device-GRE Device Gathering, Reordering, Early Write Acknowledgment. In the Cortex-A76 core, a page is cacheable only if the inner memory attribute and outer memory attribute are Write Back. In all other cases, all pages are downgraded to Non-cacheable Normal memory.
Page 69 A5.6 Specific behaviors on aborts and memory attributes See the Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile for more ® information on translation table formats. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A5-69 reserved. Non-Confidential...
Page 70 A5 Memory Management Unit A5.6 Specific behaviors on aborts and memory attributes 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. A5-70 Non-Confidential...
Page 71: Chapter A6
• A6.4 L1 data memory system on page A6-77. • A6.5 Data prefetching on page A6-79. • A6.6 Direct access to internal memory on page A6-80. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-71 reserved. Non-Confidential...
Page 72: A6.1 About The L1 Memory System
• Two 128-bit read paths from the data L1 memory system to the datapath. • 256-bit write path from the datapath to the L1 memory system. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-72 reserved. Non-Confidential...
Page 73: A6.2 Cache Behavior
The L1 instruction and data caches are invalidated automatically at reset unless the DISCACHEINVLD signal is set HIGH when the Cortex-A76 core is reset. This signal must only be used in diagnostic mode. If caches are not invalidated on reset, their functionality cannot be guaranteed. See the Arm DynamIQ ®...
Page 74 A6.2.5 Data cache coherency To maintain data coherency between multiple cores, the Cortex-A76 core uses the MESI protocol. A6.2.6 Write streaming mode A cache line is allocated to the L1 on either a read miss or a write miss.
Page 75: A6.3 L1 Instruction Memory System
A6.3.1 Program flow prediction The Cortex-A76 core contains program flow prediction hardware, also known as branch prediction. Branch prediction increases overall performance and reduces power consumption. With program flow prediction disabled, all taken branches incur a penalty that is associated with flushing the pipeline.
Page 76 As exception return instructions can change core privilege mode and security state, they are not predicted. These include: • ERET 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-76 reserved. Non-Confidential...
Page 77: A6.4 L1 Data Memory System
The Cortex-A76 core supports atomics to device or non-cacheable memory, however this relies on the interconnect also supporting atomics. If such an atomic instruction is executed when the interconnect does not support them, it will result in an abort.
Page 78 Transient memory. A6.4.2 Internal exclusive monitor The Cortex-A76 core L1 memory system has an internal exclusive monitor. This monitor is a 2-state, open and exclusive, state machine that manages Load-Exclusive or Store- Exclusive accesses and Clear-Exclusive ( ) instructions. You can use these instructions to construct...
Page 79: A6.5 Data Prefetching
The Armv8-A architecture introduces a Data Cache Zero by Virtual Address ( ) instruction. DC ZVA In the Cortex-A76 core, this enables a block of 64 bytes in memory, aligned to 64 bytes in size, to be set to zero. For more information, see the Arm Architecture Reference Manual Armv8, for Armv8-A architecture ®...
Page 80: A6.6 Direct Access To Internal Memory
A6.6 Direct access to internal memory The Cortex-A76 core provides a mechanism to read the internal memory that is used by the L1 caches, L2 cache, and TLB structures through implementation defined system registers. This functionality can be useful when debugging software or hardware issues.
Page 81 RAMID = 0x05 [31:24] [23:10] Reserved [9:4] Index [5:0] [3:0] Reserved The following table shows the data that is returned from accessing the L1 instruction tag RAM. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-81 reserved. Non-Confidential...
Page 82 Instruction Register 1 [63:18] [17:0] Data [81:64] Instruction Register 2 [63:0] The following table shows the data that is returned from accessing the L1 GHB RAM. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-82 reserved. Non-Confidential...
Page 83 Instruction Register 1 [63:32] [31:0] Data [95:64] Instruction Register 2 [63:0] The following table shows the data that is returned from accessing the L1 instruction TLB RAM. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-83 reserved. Non-Confidential...
Page 84 Translation regime: Secure EL1/EL0 Secure EL3 Non-secure EL1/EL0 Non-secure EL2 [4:1] TLB attribute Valid Instruction Register 1 [60] Non-secure [59:32] Physical address [39:12] [31:0] Virtual address[48:17] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-84 reserved. Non-Confidential...
Page 85 Table A6-15 L1 data cache data location encoding Bit fields of Rd Description [31:24] RAMID = 0x09 [23:20] Reserved [19:18] [17:16] BankSel [15:14] Unused [13:6] Index [13:6] [5:0] Reserved 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-85 reserved. Non-Confidential...
Page 86 Data Register 1 [63:0] Data Register 2 [63:0] The following table shows the data that is returned from accessing the L1 data cache tag RAM without ECC. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-86 reserved. Non-Confidential...
Page 87 Data Register 1 [63:0] Word3_data [31:0], Word2_data [31:0] Data Register 2 [63:0] The following table shows the data that is returned from accessing the L1 data TLB RAM. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-87 reserved. Non-Confidential...
Page 88 Physical address [39:12] [34:0] Virtual address[48:14] A6.6.3 Encoding for the L2 unified cache The following tables show the encoding required to select a given cache line. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-88 reserved. Non-Confidential...
Page 89 [5:0] Reserved The following table shows the data that is returned from accessing the L2 tag RAM when L2 is configured with a 128KB cache size. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-89 reserved. Non-Confidential...
Page 90 Data Register 2 [63:0] The following table shows the data that is returned from accessing the L2 tag RAM when L2 is configured with a 256KB cache size. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-90 reserved. Non-Confidential...
Page 91 Data Register 2 [63:0] The following table shows the data that is returned from accessing the L2 tag RAM when L2 is configured with a 512KB cache size. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-91 reserved. Non-Confidential...
Page 92 The following table shows the data that is returned from accessing the L2 victim RAM. Table A6-29 L2 victim format Register Bit field Description Data Register 0 [63:7] [6:0] PLRU [6:0] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-92 reserved. Non-Confidential...
Page 93 [23:21] Reserved [20:18] way0 way1 way2 way3 way4 [17:8] Reserved [7:0] Index The following table shows the data that is returned from accessing the L2 TLB. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-93 reserved. Non-Confidential...
Page 94 [5:2] This bit field contains the valid bits for four contiguous pages. If the entry is non- coalesced, then 0b0001 indicates a valid entry. [1:0] Reserved 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-94 reserved. Non-Confidential...
Page 95 Walk cache entry [36] Prefetched translation [35:7] Virtual address [48:20] Non-secure [5:0] Reserved Instruction Register 2 [63:8] Reserved [7:6] Translation regime: Secure EL1 Non-secure EL1 [5:0] VMID [15:10] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A6-95 reserved. Non-Confidential...
Page 97: Chapter A7
A7.1 About the L2 memory system on page A7-98. • A7.2 About the L2 cache on page A7-99. • A7.3 Support for memory types on page A7-100. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A7-97 reserved. Non-Confidential...
Page 98: A7.1 About The L2 Memory System
Configurable CHI interface to the DSU or CHI compliant system with support for 128-bit and 256-bit data widths. • Dynamic biased replacement policy. • Modified Exclusive Shared Invalid (MESI) coherency. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A7-98 reserved. Non-Confidential...
Page 99: A7.2 About The L2 Cache
The L2 cache is invalidated automatically at reset unless the DISCACHEINVLD signal is set HIGH when the Cortex-A76 core is reset. This signal must be used only in diagnostic mode. If caches are not invalidated on reset, their functionality cannot be guaranteed. See the Arm...
Page 100: A7.3 Support For Memory Types
Memory that is marked Outer Write-Through or Outer Non-cacheable is downgraded to Non- cacheable, even if the inner attributes are Write-Back cacheable. The following table shows the transaction capabilities of the Cortex-A76 core. It lists the maximum possible values for read, write, DVM issuing, and snoop capabilities of the private L2 cache.
Page 101: Reliability, Availability, And Serviceability (Ras)
Chapter A8 Reliability, Availability, and Serviceability (RAS) This chapter describes the RAS features implemented in the Cortex-A76 core. It contains the following sections: • A8.1 Cache ECC and parity on page A8-102. • A8.2 Cache protection behavior on page A8-103.
Page 102: A8.1 Cache Ecc And Parity
The Cortex-A76 core implements the RAS extension to the Armv8-A architecture which provides mechanisms for standardized reporting of the errors generated by cache protection mechanisms. When configured with core cache protection, the Cortex-A76 core can detect and correct a 1-bit error in any RAM and detect 2-bit errors in some RAMs.
Page 103: Cache Protection Behavior
The configuration of the RAS extension that is implemented in the Cortex-A76 core includes cache protection. In this case, the Cortex-A76 core protects against errors that result in a RAM bitcell holding the incorrect value. The RAMs in the Cortex-A76 core have the following capability: Single Error Detect.
Page 104 To ensure that progress is guaranteed even in case of hard error, the core returns corrected data to the core, and no cache access is required after data correction. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A8-104 reserved.
Page 105: A8.3 Uncorrected Errors And Data Poisoning
In this case, the line is invalidated and an error recovery interrupt is generated to notify software that data has potentially been lost. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A8-105 reserved.
Page 106: A8.4 Ras Error Types
When a component accesses memory, an error might be detected in that memory and then be corrected, deferred, or detected but silently propagated. The following table lists the types of RAS errors that are supported in the Cortex-A76 core. Table A8-2 RAS error types supported in the Cortex-A76 core RAS error type Definition Corrected A Corrected Error (CE) is reported for a single-bit ECC error on any protected RAM.
Page 107: A8.5 Error Synchronization Barrier
B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1 on page B2-194. • B2.51 HCR_EL2, Hypervisor Configuration Register, EL2 on page B2-212. • B2.101 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2 on page B2-286. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A8-107 reserved. Non-Confidential...
Page 108: A8.6 Error Recording
A8.6 Error recording The component that detects an error is called a node. The Cortex-A76 core is a node that interacts with the DynamIQ Shared Unit node. There is one record per node for the errors detected. For more information on error recording generated by cache protection, see the Arm Reliability, ®...
Page 109: A8.7 Error Injection
A8.7 Error injection A8.7 Error injection To support testing of error handling software, the Cortex-A76 core can inject errors in the error detection logic. The following table describes all the possible types of error that the core can encounter and therefore inject.
Page 110 A8 Reliability, Availability, and Serviceability (RAS) A8.7 Error injection 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. A8-110 Non-Confidential...
Page 111: Chapter A9
Chapter A9 Generic Interrupt Controller CPU interface This chapter describes the Cortex-A76 core implementation of the Arm Generic Interrupt Controller (GIC) CPU interface. It contains the following sections: • A9.1 About the Generic Interrupt Controller CPU interface on page A9-112.
Page 112: A9.1 About The Generic Interrupt Controller Cpu Interface
A9.1 About the Generic Interrupt Controller CPU interface The Cortex-A76 core implements the GIC CPU interface as described in the Arm Generic Interrupt Controller Architecture Specification. This interfaces with an external GICv3 or GICv4 distributor component within the cluster system and is a resource for supporting and managing interrupts.
Page 113: A9.2 Bypassing The Cpu Interface
A9.2 Bypassing the CPU interface The GIC CPU Interface is always implemented within the Cortex-A76 core. However, you can disable it if you assert the GICCDISABLE signal HIGH at reset. If you disable the GIC CPU interface, the input pins nVIRQ and nVFIQ can be driven by an external GIC in the SoC. GIC...
Page 114 A9 Generic Interrupt Controller CPU interface A9.2 Bypassing the CPU interface 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. A9-114 Non-Confidential...
Page 115: Chapter A10
It contains the following sections: • A10.1 About the Advanced SIMD and floating-point support on page A10-116. • A10.2 Accessing the feature identification registers on page A10-117. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights A10-115 reserved. Non-Confidential...
Page 116: A10.1 About The Advanced Simd And Floating-Point Support
A10.1 About the Advanced SIMD and floating-point support A10.1 About the Advanced SIMD and floating-point support The Cortex-A76 core supports the Advanced SIMD and scalar floating-point instructions in the A64 instruction set and the Advanced SIMD and floating-point instructions in the A32 and T32 instruction sets.
Page 117: A10.2 Accessing The Feature Identification Registers
Software can identify the Advanced SIMD and floating-point features using the feature identification registers in the AArch64 Execution state only. The Cortex-A76 core only supports AArch32 in EL0, therefore none of the feature identification registers are accessible in the AArch32 Execution state.
Page 118 A10 Advanced SIMD and floating-point support A10.2 Accessing the feature identification registers 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. A10-118 Non-Confidential...
Page 119 Part B Register descriptions...
Page 121: Chapter B1
AArch32 system registers This chapter describes the system registers in the AArch32 state. It contains the following section: • B1.1 AArch32 architectural system register summary on page B1-122. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B1-121 reserved. Non-Confidential...
Page 122: B1.1 Aarch32 Architectural System Register Summary
B1.1 AArch32 architectural system register summary This chapter identifies the AArch32 architectural system registers implemented in the Cortex-A76 core. The following table identifies the architecturally defined registers that are implemented in the Cortex-A76 core. For a description of these registers see the Arm Architecture Reference Manual ®...
Page 123: Chapter B2
B2.21 CPTR_EL2, Architectural Feature Trap Register, EL2 on page B2-164. • B2.22 CPTR_EL3, Architectural Feature Trap Register, EL3 on page B2-165. • B2.23 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1 on page B2-166. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-123 reserved. Non-Confidential...
Page 124 B2-252. • B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1 on page B2-254. • B2.77 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1 on page B2-256. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-124 reserved. Non-Confidential...
Page 125 B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register on page B2-287. • B2.103 VTCR_EL2, Virtualization Translation Control Register, EL2 on page B2-288. • B2.104 VTTBR_EL2, Virtualization Translation Table Base Register, EL2 on page B2-289. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-125 reserved. Non-Confidential...
Page 126: B2.1 Aarch64 Registers
AArch64 architectural system register summary This section identifies the AArch64 architectural system registers implemented in the Cortex-A76 core that have implementation defined bit fields. The register descriptions for these registers only contain information about the implementation defined bits. AArch64 implementation defined register summary This section identifies the AArch64 architectural registers implemented in the Cortex-A76 core that are implementation defined.
Page 127: Aarch64 Architectural System Register Summary
B2.2 AArch64 architectural system register summary B2.2 AArch64 architectural system register summary This section describes the AArch64 architectural system registers implemented in the Cortex-A76 core. The section contains two tables: Registers with implementation defined bit fields This table identifies the architecturally defined registers in Cortex-A76 that have implementation defined bit fields.
Page 128 B2.50 HACR_EL2, Hyp Auxiliary Configuration Register, EL2 on page B2-211 HCR_EL2 B2.51 HCR_EL2, Hypervisor Configuration Register, EL2 on page B2-212 ID_AFR0_EL1 B2.63 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0, EL1 on page B2-230 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-128 reserved. Non-Confidential...
Page 129 B2.58 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1 on page B2-222 ID_AA64MMFR1_EL1 3 B2.59 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1 on page B2-224 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-129 reserved. Non-Confidential...
Page 130 B2-282 TTBR0_EL3 B2.98 TTBR0_EL3, Translation Table Base Register 0, EL3 on page B2-283 TTBR1_EL1 B2.99 TTBR1_EL1, Translation Table Base Register 1, EL1 on page B2-284 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-130 reserved. Non-Confidential...
Page 131 Counter-timer Physical Timer TimerValue register CNTP_TVAL_EL02 Counter-timer Physical Timer TimerValue register CNTPCT_EL0 Counter-timer Physical Count register CNTPS_CTL_EL1 Counter-timer Physical Secure Timer Control register CNTPS_CVAL_EL1 Counter-timer Physical Secure Timer CompareValue register 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-131 reserved. Non-Confidential...
Page 132 LORegion Start Address Register MAIR_EL1 Memory Attribute Indirection Register (EL1) MAIR_EL12 Memory Attribute Indirection Register (EL12) MAIR_EL2 Memory Attribute Indirection Register (EL2) MAIR_EL3 Memory Attribute Indirection Register (EL3) 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-132 reserved. Non-Confidential...
Page 133 Vector Base Address Register (EL12) VBAR_EL2 Vector Base Address Register (EL2) VBAR_EL3 Vector Base Address Register (EL3) VMPIDR_EL2 Virtualization Multiprocessor ID Register VPIDR_EL2 Virtualization Core ID Register 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-133 reserved. Non-Confidential...
Page 134: B2.3 Aarch64 Implementation Defined Register Summary
B2.3 AArch64 implementation defined register summary B2.3 AArch64 implementation defined register summary This section describes the AArch64 registers in the Cortex-A76 core that are implementation defined. The following tables lists the AArch 64 implementation defined registers, sorted by opcode. Table B2-3 AArch64 implementation defined registers...
Page 135 CLUSTERPMCEID1_EL1 32-bit Cluster Common Event Identification ID1 Register CLUSTERPMCLAIMSET_EL1 32-bit Cluster Performance Monitor Claim Tag Set Register CLUSTERPMCLAIMCLR_EL1 32-bit Cluster Performance Monitor Claim Tag Clear Register 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-135 reserved. Non-Confidential...
Page 136: Aarch64 Registers By Functional Group
B2.58 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1 on page B2-222 ID_AA64MMFR1_EL1 RO 0x0000000010212122 B2.59 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1 on page B2-224 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-136 reserved. Non-Confidential...
Page 137 B2.75 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1 on page B2-252 ID_MMFR4_EL1 0x00021110 B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1 on page B2-254 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-137 reserved. Non-Confidential...
Page 138 B2.91 SCTLR_EL2, System Control Register, EL2 on page B2-275 SCTLR_EL3 B2.92 SCTLR_EL3, System Control Register, EL3 on page B2-276 SCTLR_EL12 RW B2.90 SCTLR_EL1, System Control Register, EL1 on page B2-273 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-138 reserved. Non-Confidential...
Page 139 B2.80 LORC_EL1, LORegion Control Register, EL1 on page B2-261 LOREA_EL1 RW LORegion End Address Register EL1 LORID_EL1 RO B2.81 LORID_EL1, LORegion ID Register, EL1 on page B2-262 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-139 reserved. Non-Confidential...
Page 140 B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register on page B2-287 VTCR_EL2 B2.103 VTCR_EL2, Virtualization Translation Control Register, EL2 on page B2-288 VTTBR_EL2 B2.104 VTTBR_EL2, Virtualization Translation Table Base Register, EL2 on page B2-289 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-140 reserved. Non-Confidential...
Page 141 B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1 on page B2-204 ERXPFGFR_EL1 B2.45 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1 on page B2-206 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-141 reserved. Non-Confidential...
Page 142 Cluster Selected Event Counter Register Reserved/RAZ 32-bit Cluster Monitor Debug Configuration Register CLUSTERPMCEID0_EL1 32-bit Cluster Common Event Identification ID0 Register CLUSTERPMCEID1_EL1 32-bit Cluster Common Event Identification ID1 Register 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-142 reserved. Non-Confidential...
Page 143 B2.89 RVBAR_EL3, Reset Vector Base Address Register, EL3 on page B2-272 Address registers Name Type Description PAR_EL1 RW B2.86 PAR_EL1, Physical Address Register, EL1 on page B2-269 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-143 reserved. Non-Confidential...
Page 144: B2.5 Actlr_El1, Auxiliary Control Register, El1
There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-144 reserved. Non-Confidential...
Page 145: B2.6 Actlr_El2, Auxiliary Control Register, El2
CLUSTERBUSQOS, and CLUSTERTHREADSIDOVR are write-accessible from EL1 Non-secure if they are write-accessible from EL2. RES0, [9:8] Reserved. RES0 PWREN, [7] Power Control Registers enable. The possible values are: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-145 reserved. Non-Confidential...
Page 146 Configurations Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-146 reserved. Non-Confidential...
Page 147: B2.7 Actlr_El3, Auxiliary Control Register, El3
Register CLUSTERTHREADSID is not write-accessible from EL2 and EL1 Secure. This is the reset value. Register CLUSTERTHREADSID is write-accessible from EL2 and EL1 Secure. RES0, [9:8] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-147 reserved. Non-Confidential...
Page 148 Configurations Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-148 reserved. Non-Confidential...
Page 149: B2.8 Afsr0_El1, Auxiliary Fault Status Register 0, El1
AFSR0_EL1 provides additional fault status information for exceptions that are IMPLEMENTATION DEFINED taken to EL1. In the Cortex-A76 core, no additional information is provided for these exceptions. Therefore this register is not used. Bit field descriptions AFSR0_EL1 is a 32-bit register, and is part of: •...
Page 150: B2.9 Afsr0_El2, Auxiliary Fault Status Register 0, El2
There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-150 reserved. Non-Confidential...
Page 151: B2.10 Afsr0_El3, Auxiliary Fault Status Register 0, El3
AFSR0_EL3 provides additional fault status information for exceptions that are IMPLEMENTATION DEFINED taken to EL3. In the Cortex-A76 core, no additional information is provided for these exceptions. Therefore this register is not used. Bit field descriptions AFSR0_EL3 is a 32-bit register, and is part of: •...
Page 152: B2.11 Afsr1_El1, Auxiliary Fault Status Register 1, El1
There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-152 reserved. Non-Confidential...
Page 153: B2.12 Afsr1_El2, Auxiliary Fault Status Register 1, El2
AFSR1_EL2, Auxiliary Fault Status Register 1, EL2 AFSR1_EL2 provides additional fault status information for exceptions that are IMPLEMENTATION DEFINED taken to EL2. This register is not used in the Cortex-A76 core. Bit field descriptions AFSR1_EL2 is a 32-bit register, and is part of: •...
Page 154: B2.13 Afsr1_El3, Auxiliary Fault Status Register 1, El3
AFSR1_EL3, Auxiliary Fault Status Register 1, EL3 AFSR1_EL3 provides additional fault status information for exceptions that are IMPLEMENTATION DEFINED taken to EL3. This register is not used in the Cortex-A76 core. Bit field descriptions AFSR1_EL3 is a 32-bit register, and is part of: •...
Page 155: B2.14 Aidr_El1, Auxiliary Id Register, El1
There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-155 reserved. Non-Confidential...
Page 156: B2.15 Amair_El1, Auxiliary Memory Attribute Indirection Register, El1
AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1 AMAIR_EL1 provides memory attributes for the memory regions specified by IMPLEMENTATION DEFINED MAIR_EL1. This register is not used in the Cortex-A76 core. Bit field descriptions AMAIR_EL1 is a 64-bit register, and is part of: •...
Page 157: B2.16 Amair_El2, Auxiliary Memory Attribute Indirection Register, El2
AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2 AMAIR_EL2 provides memory attributes for the memory regions specified by IMPLEMENTATION DEFINED MAIR_EL2. This register is not used in the Cortex-A76 core. Bit field descriptions AMAIR_EL2 is a 64-bit register, and is part of: •...
Page 158: B2.17 Amair_El3, Auxiliary Memory Attribute Indirection Register, El3
AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3 AMAIR_EL3 provides memory attributes for the memory regions specified by IMPLEMENTATION DEFINED MAIR_EL3. This register is not used in the Cortex-A76 core. Bit field descriptions AMAIR_EL3 is a 64-bit register, and is part of: •...
Page 159: B2.18 Ccsidr_El1, Cache Size Id Register, El1
(Number of sets in cache) - 1. Therefore, a value of 0 indicates one set in the cache. The number of sets does not have to be a power of 2. For more information about encoding, see CCSIDR_EL1 encodings on page B2-160. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-159 reserved. Non-Confidential...
Page 160 0b001 128KB 701FE03A 0x00FF 0x007 L2 cache 256KB 703FE03A 0x01FF 0x007 512KB 707FE03A 0x03FF 0x007 0b001 Reserved 0b010 Reserved 0b010 Reserved 0b0101 - 0b1111 Reserved 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-160 reserved. Non-Confidential...
Page 161: B2.19 Clidr_El1, Cache Level Id Register, El1
No cache at levels L7 down to L4. Reserved. RES0 Ctype3, [8:6] Indicates the type of cache if the core implements L3 cache. If present, unified instruction and data caches at Level 3: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-161 reserved. Non-Confidential...
Page 162 There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-162 reserved. Non-Confidential...
Page 163: B2.20 Cpacr_El1, Architectural Feature Access Control Register, El1
Configurations Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-163 reserved. Non-Confidential...
Page 164: B2.21 Cptr_El2, Architectural Feature Trap Register, El2
RW fields in this register reset to UNKNOWN values. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-164 reserved. Non-Confidential...
Page 165: B2.22 Cptr_El3, Architectural Feature Trap Register, El3
There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-165 reserved. Non-Confidential...
Page 166: B2.23 Cpuactlr_El1, Cpu Auxiliary Control Register, El1
Usage constraints Accessing the CPUACTLR_EL1 The CPU Auxiliary Control Register can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled. Setting many of these bits can cause significantly lower performance on your code. Therefore, Arm strongly recommends that you do not modify this register unless directed by Arm.
Page 167 For a description of the prioritization of any generated exceptions, see Synchronous exception prioritization in the Arm Architecture Reference Manual Armv8, for Armv8-A architecture ® profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-167 reserved. Non-Confidential...
Page 168: B2.24 Cpuactlr2_El1, Cpu Auxiliary Control Register 2, El1
Usage constraints Accessing the CPUACTLR2_EL1 The CPUACTLR2_EL1 can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled. Setting many of these bits can cause significantly lower performance on your code. Therefore, Arm strongly recommends that you do not modify this register unless directed by Arm.
Page 169 AArch64 state, and see Synchronous exception prioritization for exceptions taken to AArch64 state. Write access to this register from EL1 or EL2 depends on the value of bit[0] of ACTLR_EL2 and ACTLR_EL3. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-169 reserved. Non-Confidential...
Page 170: B2.25 Cpucfr_El1, Cpu Configuration Register, El1
This syntax is encoded with the following settings in the instruction encoding: <systemreg> op0 op1 CRn CRm op2 S3_0_C15_C0_0 11 000 1111 0000 Accessibility This register is accessible in software as follows: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-170 reserved. Non-Confidential...
Page 171 B2.25 CPUCFR_EL1, CPU Configuration Register, EL1 <systemreg> Control Accessibility S3_0_C15_C0_0 S3_0_C15_C0_0 S3_0_C15_C0_0 'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-171 reserved. Non-Confidential...
Page 172: B2.26 Cpuectlr_El1, Cpu Extended Control Register, El1
Figure B2-22 CPUECTLR_EL1 bit assignments RES0, [63:62] Reserved. RES0 MXP_EN, [61] Max-power throttle enable. The possible values are: Disables max-power throttling mechanism. This is the reset value. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-172 reserved. Non-Confidential...
Page 173 Disables L2 TLB prefetcher. The possible values are: Enables L2 TLB prefetcher. This is the reset value. Disables L2 TLB prefetcher. HPA_MODE, [50:49] Hardware Page Aggregation (HPA) mode. The possible values are: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-173 reserved. Non-Confidential...
Page 174 Aggressively generate prefetchtgt for cacheable requests from the MMU, always generate for non-cacheable. Always generate prefetchtgt for cacheable requests from the MMU, always generate for non-cacheable. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-174 reserved. Non-Confidential...
Page 175 Acquire-atomic is near if cache line is already Exclusive, otherwise make far atomic request. Acquire-atomic will make up to 1 fill request to perform near. This is the reset value. ATOMIC_ST_NEAR, [31] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-175 reserved. Non-Confidential...
Page 176 Threshold for direct stream to L3 cache on store. The possible values are: 768B. 16KB. This is the reset value. 32KB. Disables direct stream to L3 cache on store. WS_THR_L4, [21:20] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-176 reserved. Non-Confidential...
Page 177 RES0, [9] Reserved. RES0 PF_STI_DIS, [8] Disables store prefetches at issue (not overriden by CPUECTLR_EL1[15]). The possible values are: Enables store prefetching. This is the reset value. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-177 reserved. Non-Confidential...
Page 178 DataSource field on the master CHI interface indicates when data is returned from the LLC. This is used to control how the LL_CACHE* PMU events count. Configurations This register has no configuration options. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-178 reserved. Non-Confidential...
Page 179 Usage constraints Accessing the CPUECTLR_EL1 The CPU Extended Control Register can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled. This register can be read using MRS with the following syntax: MRS <Xt>,<systemreg>...
Page 180: B2.27 Cpupcr_El3, Cpu Private Control Register, El3
CPUPCR_EL3 is only accessible in Secure state. Usage constraints Accessing the CPUPCR_EL3 The CPUPCR_EL3 can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled. Writing to this register might cause behaviors.
Page 181 For a description of the prioritization of any generated exceptions, see Synchronous exception prioritization in the Arm Architecture Reference Manual Armv8, for Armv8-A architecture ® profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-181 reserved. Non-Confidential...
Page 182: B2.28 Cpupmr_El3, Cpu Private Mask Register, El3
CPUPMR_EL3 is only accessible in Secure state. Usage constraints Accessing the CPUPMR_EL3 The CPUPMR_EL3 can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled. Writing to this register might cause behaviors.
Page 183 For a description of the prioritization of any generated exceptions, see Synchronous exception prioritization in the Arm Architecture Reference Manual Armv8, for Armv8-A architecture ® profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-183 reserved. Non-Confidential...
Page 184: B2.29 Cpupor_El3, Cpu Private Operation Register, El3
CPUPOR_EL3 is only accessible in Secure state. Usage constraints Accessing the CPUPOR_EL3 The CPUPOR_EL3 can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled. Writing to this register might cause behaviors.
Page 185 For a description of the prioritization of any generated exceptions, see Synchronous exception prioritization in the Arm Architecture Reference Manual Armv8, for Armv8-A architecture ® profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-185 reserved. Non-Confidential...
Page 186: B2.30 Cpupselr_El3, Cpu Private Selection Register, El3
CPUPSELR_EL3 is only accessible in Secure state. Usage constraints Accessing the CPUPSELR_EL3 The CPUPSELR_EL3 can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled. Writing to this register might cause behaviors.
Page 187 For a description of the prioritization of any generated exceptions, see Synchronous exception prioritization in the Arm Architecture Reference Manual Armv8, for Armv8-A architecture ® profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-187 reserved. Non-Confidential...
Page 188: B2.31 Cpupwrctlr_El1, Power Control Register, El1
The number of system counter ticks required before the core signals retention readiness on PACTIVE to the power controller. The core does not accept a retention entry request until this time. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-188 reserved.
Page 189 The number of system counter ticks required before the core signals retention readiness on PACTIVE to the power controller. The core does not accept a retention entry request until this time. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-189 reserved.
Page 190: B2.32 Csselr_El1, Cache Size Selection Register, El1
If a cache level is missing but CSSELR_EL1 selects this level, then a CCSIDR_EL1 read returns an value. UNKNOWN Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 191: B2.33 Ctr_El0, Cache Type Register, El0
Smallest data cache line size is 16 words. 0100 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-191 reserved. Non-Confidential...
Page 192 Smallest instruction cache line size is 16 words. 0100 Configurations There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 193: B2.34 Dczid_El0, Data Cache Zero Id Register, El0
The block size is 16 words. 0100 Configurations There are no configuration notes. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-193 reserved.
Page 194: B2.35 Disr_El1, Deferred Interrupt Status Register, El1
EA, [9] Reserved, RES0 RES0, [8:6] Reserved, RES0 DFSC, [5:0] Data Fault Status Code. The possible values of this field are: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-194 reserved. Non-Confidential...
Page 195 SError interrupt. The Parity Error codes are not used in the RAS extension. Configurations There are no configuration notes. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 196: B2.36 Erridr_El1, Error Id Register, El1
Two records present. 0x0002 Configurations There are no configuration notes. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-196 reserved.
Page 197: B2.37 Errselr_El1, Error Record Select Register, El1
Select record 1 containing errors from Level 3 RAMs located on the DSU. Configurations There are no configuration notes. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 198: B2.38 Erxaddr_El1, Selected Error Record Address Register, El1
B3.2 ERR0ADDR, Error Record Address Register on page B3-293. If ERRSELR_EL1.SEL==1, then ERXADDR_EL1 accesses the ERR1ADDR register of the DSU error record. See the Arm DynamIQ Shared Unit Technical Reference Manual. ® ™ 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-198 reserved. Non-Confidential...
Page 199: B2.39 Erxctlr_El1, Selected Error Record Control Register, El1
B3.3 ERR0CTLR, Error Record Control Register on page B3-294. If ERRSELR_EL1.SEL==1, then ERXCLTR_EL1 accesses the ERR1CTLR register of the DSU error record. See the Arm DynamIQ Shared Unit Technical Reference Manual. ® ™ 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-199 reserved. Non-Confidential...
Page 200: B2.40 Erxfr_El1, Selected Error Record Feature Register, El1
B3.4 ERR0FR, Error Record Feature Register on page B3-296. If ERRSELR_EL1.SEL==1, then ERXFR_EL1 accesses the ERR1FR register of the DSU error record. See the Arm DynamIQ Shared Unit Technical Reference Manual. ® ™ 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-200 reserved. Non-Confidential...
Page 201: B2.41 Erxmisc0_El1, Selected Error Record Miscellaneous Register 0, El1
B3.5 ERR0MISC0, Error Record Miscellaneous Register 0 on page B3-298. If ERRSELR_EL1.SEL==1, then ERXMISC0_EL1 accesses the ERR1MISC0 register of the DSU error record. See the Arm DynamIQ Shared Unit Technical Reference Manual. ® ™ 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-201 reserved. Non-Confidential...
Page 202: B2.42 Erxmisc1_El1, Selected Error Record Miscellaneous Register 1, El1
B3.6 ERR0MISC1, Error Record Miscellaneous Register 1 on page B3-301. If ERRSELR_EL1.SEL==1, then ERXMISC1_EL1 accesses the ERR1MISC1 register of the DSU error record. See the Arm DynamIQ Shared Unit Technical Reference Manual. ® ™ 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-202 reserved. Non-Confidential...
Page 203: Erxpfgcdnr_El1, Selected Error Pseudo Fault Generation Count Down Register, El1
ACTLR_EL2 and ACTLR_EL3. See B2.6 ACTLR_EL2, Auxiliary Control Register, EL2 on page B2-145 B2.7 ACTLR_EL3, Auxiliary Control Register, EL3 on page B2-147. ERXPFGCDNR_EL1 is at EL0. UNDEFINED 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-203 reserved. Non-Confidential...
Page 204 This register is accessible in software as follows: <syntax> Control Accessibility S3_0_C15_C2_1 S3_0_C15_C2_1 S3_0_C15_C2_1 'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-204 reserved. Non-Confidential...
Page 205 If ERXPFGCTLR_EL1 is accessible at EL1 or EL2 and SCR_EL3.TERR == 1, then direct reads and writes of ERXPFGCTLR_EL1 at EL1 or EL2 generate a Trap exception to EL3. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-205 reserved.
Page 206: B2.45 Erxpfgfr_El1, Selected Pseudo Fault Generation Feature Register, El1
If ERXPFGR_EL1 is accessible at EL1 or EL2 and SCR_EL3.TERR == 1, then direct reads and writes of ERXPFGR_EL1 at EL1 or EL2 generate a Trap exception to EL3. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-206 reserved.
Page 207: B2.46 Erxstatus_El1, Selected Error Record Primary Status Register, El1
B3.10 ERR0STATUS, Error Record Primary Status Register on page B3-307. If ERRSELR_EL1.SEL==1, then ERXSTATUS_EL1 accesses the ERR1STATUS register of the DSU error record. See the Arm DynamIQ Shared Unit Technical Reference Manual. ® ™ 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-207 reserved. Non-Confidential...
Page 208: B2.47 Esr_El1, Exception Syndrome Register, El1
When reporting a synchronous data abort, EA is RES0 B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register on page B2-287. Configurations This register has no configuration options. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-208 reserved. Non-Confidential...
Page 209: B2.48 Esr_El2, Exception Syndrome Register, El2
Configurations RW fields in this register reset to architecturally values. UNKNOWN Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-209 reserved.
Page 210: B2.49 Esr_El3, Exception Syndrome Register, El3
When reporting a synchronous data abort, EA is RES0 B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register on page B2-287. Configurations RW fields in this register reset to architecturally UNKNOWN values. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-210 reserved. Non-Confidential...
Page 211: B2.50 Hacr_El2, Hyp Auxiliary Configuration Register, El2
Reserved, RES0 Configurations There are no configuration notes. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-211 reserved.
Page 212: B2.51 Hcr_El2, Hypervisor Configuration Register, El2
RES0, [63:39] Reserved. RES0 MIOCNCE, [38] Mismatched Inner/Outer Cacheable Non-Coherency Enable, for the Non-secure EL1 and EL0 translation regime. RW, [31] Reserved. RES1 HCD, [29] Reserved. RES0 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-212 reserved. Non-Confidential...
Page 213 RES0 RW fields in this register reset to architecturally values. UNKNOWN Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-213 reserved.
Page 214: B2.52 Id_Aa64Afr0_El1, Aarch64 Auxiliary Feature Register 0
B2 AArch64 system registers B2.52 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0 B2.52 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0 The core does not use this register, ID_AA64AFR0_EL1 is RES0 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-214 reserved. Non-Confidential...
Page 215: B2.53 Id_Aa64Afr1_El1, Aarch64 Auxiliary Feature Register 1
B2 AArch64 system registers B2.53 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1 B2.53 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1 The core does not use this register, ID_AA64AFR0_EL1 is RES0 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-215 reserved. Non-Confidential...
Page 216: B2.54 Id_Aa64Dfr0_El1, Aarch64 Debug Feature Register 0, El1
Performance Monitors Extension version. Performance monitor system registers implemented, PMUv3. TraceVer, [7:4] Trace extension: Trace system registers not implemented. DebugVer, [3:0] Debug architecture version: Armv8-A debug architecture implemented. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-216 reserved. Non-Confidential...
Page 217 ID_AA64DFR0_EL1 is architecturally mapped to external register EDDFR. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-217 reserved. Non-Confidential...
Page 218: B2.55 Id_Aa64Dfr1_El1, Aarch64 Debug Feature Register 1, El1
B2.55 ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1, EL1 This register is reserved for future expansion of top level information about the debug system in AArch64 state. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-218 reserved. Non-Confidential...
Page 219: B2.56 Id_Aa64Isar0_El1, Aarch64 Instruction Set Attribute Register 0, El1
ID_AA64ISAR0_EL1 is a 64-bit register, and is part of the Identification registers functional group. This register is Read Only. The optional Cryptographic Extension is not included in the base product of the core. Arm requires licensees to have contractual rights to obtain the Cryptographic Extension.
Page 220 ID_AA64ISAR0_EL1 is architecturally mapped to external register ID_AA64ISAR0. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-220 reserved. Non-Confidential...
Page 221: B2.57 Id_Aa64Isar1_El1, Aarch64 Instruction Set Attribute Register 1, El1
There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-221 reserved. Non-Confidential...
Page 222: B2.58 Id_Aa64Mmfr0_El1, Aarch64 Memory Model Feature Register 0, El1
Supports a distinction between Secure and Non-secure Memory. BigEnd, [11:8] Mixed-endian configuration support: Mixed-endian support. The SCTLR_ELx.EE and SCTLR_EL1.E0E bits can be configured. ASIDBits, [7:4] Number of ASID bits: 16 bits. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-222 reserved. Non-Confidential...
Page 223 There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-223 reserved. Non-Confidential...
Page 224: B2.59 Id_Aa64Mmfr1_El1, Aarch64 Memory Model Feature Register 1, El1
The value is: IMPLEMENTATION DEFINED Hierarchical Permission Disables and Hardware allocation of bits[62:59] supported. VH, [11:8] Indicates whether Virtualization Host Extensions are supported. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-224 reserved. Non-Confidential...
Page 225 There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-225 reserved. Non-Confidential...
Page 226: B2.60 Id_Aa64Mmfr2_El1, Aarch64 Memory Model Feature Register 2, El1
There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-226 reserved. Non-Confidential...
Page 227: B2.61 Id_Aa64Pfr0_El1, Aarch64 Processor Feature Register 0, El1
The ID_AA64PFR0_EL1 provides additional information about implemented core features in AArch64. The optional Advanced SIMD and floating-point support is not included in the base product of the core. Arm requires licensees to have contractual rights to obtain the Advanced SIMD and floating-point support.
Page 228 ID_AA64PFR0_EL1 is architecturally mapped to External register EDPFR. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-228 reserved. Non-Confidential...
Page 229: B2.62 Id_Aa64Pfr1_El1, Aarch64 Processor Feature Register 1, El1
ID_AA64PFR1_EL1 is architecturally mapped to External register EDPFR. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-229 reserved. Non-Confidential...
Page 230: B2.63 Id_Afr0_El1, Aarch32 Auxiliary Feature Register 0, El1
Reserved, RES0 Configurations There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-230 reserved.
Page 231: B2.64 Id_Dfr0_El1, Aarch32 Debug Feature Register 0, El1
Indicates support for coprocessor-based Secure debug model: This product supports the Armv8.2 Debug architecture. CopDbg, [3:0] Indicates support for coprocessor-based debug model: This product supports the Armv8.2 Debug architecture. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-231 reserved. Non-Confidential...
Page 232 B2.64 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1 Configurations There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 233: B2.65 Id_Isar0_El1, Aarch32 Instruction Set Attribute Register 0, El1
Indicates the implemented combined Compare and Branch instructions in the T32 instruction set: CBNZ Bitfield, [11:8] Indicates the implemented bit field instructions: , and SBFX UBFX BitCount, [7:4] Indicates the implemented Bit Counting instructions: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-233 reserved. Non-Confidential...
Page 234 • B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 on page B2-245. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 235: B2.66 Id_Isar1_El1, Aarch32 Instruction Set Attribute Register 1, El1
Indicates the implemented A profile exception-handling instructions: instructions, and the A profile forms of the instruction. Except, [7:4] Indicates the implemented exception-handling instructions in the A32 instruction set: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-235 reserved. Non-Confidential...
Page 236 • B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 on page B2-245. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 237: B2.67 Id_Isar2_El1, Aarch32 Instruction Set Attribute Register 2, El1
SMMLSR SMMUL SMMULR SMUAD SMUADX SMUSD SMUSDX instructions. Mult, [15:12] Indicates the implemented additional Multiply instructions: instructions. MultiAccessInt, [11:8] Indicates the support for interruptible multi-access instructions: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-237 reserved. Non-Confidential...
Page 238 • B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 on page B2-245. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 239: B2.68 Id_Isar3_El1, Aarch32 Instruction Set Attribute Register 3, El1
LDREXB STREXB STREXH • instructions. LDREXD STREXD SVC, [11:8] Indicates the implemented SVC instructions: instruction. SIMD, [7:4] Indicates the implemented Single Instruction Multiple Data (SIMD) instructions. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-239 reserved. Non-Confidential...
Page 240 • B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 on page B2-245. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 241: B2.69 Id_Isar4_El1, Aarch32 Instruction Set Attribute Register 4, El1
Indicates the support for Write-Back addressing modes: Core supports all the Write-Back addressing modes as defined in Armv8-A. WithShifts, [7:4] Indicates the support for instructions with shifts. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-241 reserved. Non-Confidential...
Page 242 • B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 on page B2-245. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 243: B2.70 Id_Isar5_El1, Aarch32 Instruction Set Attribute Register 5, El1
Extensions are not implemented or are disabled. , and instructions are implemented. SHA1C SHA1P SHA1M SHA1H SHA1SU0 SHA1SU1 This is the value when the Cryptographic Extensions are implemented and enabled. AES, [7:4] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-243 reserved. Non-Confidential...
Page 244 • B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 on page B2-245. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 245: B2.71 Id_Isar6_El1, Aarch32 Instruction Set Attribute Register 6, El1
B2-241. • B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1 on page B2-243. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-245 reserved.
Page 246: B2.72 Id_Mmfr0_El1, Aarch32 Memory Model Feature Register 0, El1
Implemented with hardware coherency support. PMSA, [7:4] Indicates support for a Protected Memory System Architecture (PMSA): Not supported. VMSA, [3:0] Indicates support for a Virtual Memory System Architecture (VMSA). 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-246 reserved. Non-Confidential...
Page 247 • B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1 on page B2-254. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 248: B2.73 Id_Mmfr1_El1, Aarch32 Memory Model Feature Register 1, El1
Indicates the supported L1 cache line maintenance operations by set/way, for a Harvard cache implementation: None supported. L1UniVA, [7:4] Indicates the supported L1 cache line maintenance operations by MVA, for a unified cache implementation: None supported. L1HvdVA, [3:0] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-248 reserved. Non-Confidential...
Page 249 • B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1 on page B2-254. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 250: B2.74 Id_Mmfr2_El1, Aarch32 Memory Model Feature Register 2, El1
TLBIMVAAL TLBIMVALH • , and TLBIIPAS2IS TLBIIPAS2LIS TLBIIPAS2 TLBIIPAS2L HvdTLB, [15:12] Harvard TLB. Indicates the supported TLB maintenance operations, for a Harvard TLB implementation: Not supported. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-250 reserved. Non-Confidential...
Page 251 • B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1 on page B2-254. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 252: B2.75 Id_Mmfr3_El1, Aarch32 Memory Model Feature Register 3, El1
Branch predictor maintenance. Indicates the supported branch predictor maintenance operations. Supported branch predictor maintenance operations are: • Invalidate all branch predictors. • Invalidate branch predictors by MVA. CMaintSW, [7:4] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-252 reserved. Non-Confidential...
Page 253 • B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1 on page B2-254. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 254: B2.76 Id_Mmfr4_El1, Aarch32 Memory Model Feature Register 4, El1
Describes whether the core can generate SError interrupt exceptions from speculative reads of memory, including speculative instruction fetches. The value is: The core never generates an SError interrupt due to an external abort on a speculative read. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-254 reserved. Non-Confidential...
Page 255 • B2.75 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1 on page B2-252. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 256: B2.77 Id_Pfr0_El1, Aarch32 Processor Feature Register 0, El1
Core supports T32 encoding after the introduction of Thumb-2 technology, and for all 16-bit and 32-bit T32 basic instructions. State0, [3:0] Indicates support for A32 instruction set. This value is: A32 instruction set implemented. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-256 reserved. Non-Confidential...
Page 257 B2.77 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1 Configurations There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 258: B2.78 Id_Pfr1_El1, Aarch32 Processor Feature Register 1, El1
ProgMod, [3:0] Indicates support for the standard programmers model for Armv4 and later. Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined, and System modes: Not supported. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-258 reserved. Non-Confidential...
Page 259 B2 AArch64 system registers B2.78 ID_PFR1_EL1, AArch32 Processor Feature Register 1, EL1 Configurations There are no configuration notes. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-259 reserved. Non-Confidential...
Page 260: B2.79 Id_Pfr2_El1, Aarch32 Processor Feature Register 2, El1
This is the reset value. Configurations There are no configuration notes. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-260 reserved. Non-Confidential...
Page 261: B2.80 Lorc_El1, Loregion Control Register, El1
UNKNOWN Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-261 reserved. Non-Confidential...
Page 262: B2.81 Lorid_El1, Loregion Id Register, El1
There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-262 reserved. Non-Confidential...
Page 263: B2.82 Lorn_El1, Loregion Number Register, El1
UNKNOWN Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-263 reserved. Non-Confidential...
Page 264: B2.83 Mdcr_El3, Monitor Debug Configuration Register, El3
Trap accesses to the OS debug system registers, OSLAR_EL1, OSLSR_EL1, OSDLR_EL1, and DBGPRCR_EL1 OS. Accesses are not trapped. Accesses to the OS debug system registers are trapped to EL3. The reset value is UNKNOWN 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-264 reserved. Non-Confidential...
Page 265 There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-265 reserved. Non-Confidential...
Page 266: B2.84 Midr_El1, Main Id Register, El1
The MIDR_EL1 is architecturally mapped to external MIDR_EL1 register. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-266 reserved. Non-Confidential...
Page 267: B2.85 Mpidr_El1, Multiprocessor Affinity Register, El1
Affinity0 represents threads. Cortex-A76 is not multithreaded, but may be in a system with other cores that are multithreaded. Aff2, [23:16] Affinity level 2. Second highest level affinity field. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-267 reserved. Non-Confidential...
Page 268 MP1: CPUID: 0. MP8: CPUID: 7. Aff0, [7:0] Affinity level 0. The level identifies individual threads within a multithreaded core. The Cortex-A76 core is single-threaded, so this field has the value 0x00 Configurations MPIDR_EL1[31:0] is mapped to external register EDDEVAFF0.
Page 269: B2.86 Par_El1, Physical Address Register, El1
Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® Bit field descriptions, PAR_EL1.F is 1 See the Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-269 reserved. Non-Confidential...
Page 270: B2.87 Revidr_El1, Revision Id Register, El1
REVIDR_EL1, Revision ID Register, EL1 The REVIDR_EL1 provides revision information, additional to MIDR_EL1, that identifies minor fixes (errata) which might be present in a specific implementation of the Cortex-A76 core. Bit field descriptions REVIDR_EL1 is a 32-bit register, and is part of the Identification registers functional group.
Page 271: B2.88 Rmr_El3, Reset Management Register
Reserved. RES1 Configurations There are no configuration notes. Details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-271 reserved.
Page 272: B2.89 Rvbar_El3, Reset Vector Base Address Register, El3
0x000000 core. Configurations There are no configuration notes. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-272 reserved.
Page 273: B2.90 Sctlr_El1, System Control Register, El1
ITD, [7] This field is RAZ/WI RES0, [6] Reserved. RES0 CP15BEN, [5] CP15 barrier enable. The possible values are: CP15 barrier operations disabled. Their encodings are UNDEFINED 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-273 reserved. Non-Confidential...
Page 274 There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-274 reserved. Non-Confidential...
Page 275: B2.91 Sctlr_El2, System Control Register, El2
RES0 Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-275 reserved. Non-Confidential...
Page 276: B2.92 Sctlr_El3, System Control Register, El3
Global enable for data and unifies caches. The possible values are: Disables data and unified caches. This is the reset value. Enables data and unified caches. M, [0] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-276 reserved. Non-Confidential...
Page 277 There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-277 reserved. Non-Confidential...
Page 278: B2.93 Tcr_El1, Translation Control Register, El1
UNKNOWN Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-278 reserved. Non-Confidential...
Page 279: B2.94 Tcr_El2, Translation Control Register, El2
TCR_EL1. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-279 reserved. Non-Confidential...
Page 280: B2.95 Tcr_El3, Translation Control Register, El3
There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-280 reserved. Non-Confidential...
Page 281: B2.96 Ttbr0_El1, Translation Table Base Register 0, El1
Translation table base address, bits[47:x]. Bits [x-1:1] are RES0 x is based on the value of TCR_EL1.T0SZ, the stage of translation, and the memory translation granule size. For instructions on how to calculate it, see the Arm Architecture Reference Manual Armv8, for ® Armv8-A architecture profile.
Page 282: B2.97 Ttbr0_El2, Translation Table Base Register 0, El2
Translation table base address, bits[47:x]. Bits [x-1:1] are RES0 x is based on the value of TCR_EL2.T0SZ, the stage of translation, and the memory translation granule size. For instructions on how to calculate it, see the Arm Architecture Reference Manual Arm v8, for ®...
Page 283: B2.98 Ttbr0_El3, Translation Table Base Register 0, El3
Translation table base address, bits[47:x]. Bits [x-1:1] are RES0 x is based on the value of TCR_EL1.T0SZ, the stage of translation, and the memory translation granule size. For instructions on how to calculate it, see the Arm Architecture Reference Manual Armv8, for ® Armv8-A architecture profile.
Page 284: B2.99 Ttbr1_El1, Translation Table Base Register 1, El1
CnP is not supported. CnP is supported. Configurations There are no configuration notes. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-284 reserved.
Page 285: B2.100 Ttbr1_El2, Translation Table Base Register 1, El2
B2.100 TTBR1_EL2, Translation Table Base Register 1, EL2 TTBR1_EL2 has the same format and contents as TTBR1_EL1. B2.99 TTBR1_EL1, Translation Table Base Register 1, EL1 on page B2-284. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-285 reserved. Non-Confidential...
Page 286: B2.101 Vdisr_El2, Virtual Deferred Interrupt Status Register, El2
Configurations B2.101.1 VDISR_EL2 at EL1 using AArch64 on page B2-286. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. This section contains the following subsection: •...
Page 287: B2.102 Vsesr_El2, Virtual Serror Exception Syndrome Register
There are no configuration notes. Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-287 reserved. Non-Confidential...
Page 288: B2.103 Vtcr_El2, Virtualization Translation Control Register, El2
UNKNOWN Bit fields and details that are not provided in this description are architecturally defined. See the Architecture Reference Manual Armv8, for Armv8-A architecture profile. ® 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-288 reserved. Non-Confidential...
Page 289: B2.104 Vttbr_El2, Virtualization Translation Table Base Register, El2
CnP is not supported. CnP is supported. Configurations There are no configuration notes. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B2-289 reserved.
Page 290 B2 AArch64 system registers B2.104 VTTBR_EL2, Virtualization Translation Table Base Register, EL2 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. B2-290 Non-Confidential...
Page 291 B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register on page B3-303. • B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register on page B3-305. • B3.10 ERR0STATUS, Error Record Primary Status Register on page B3-307. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-291 reserved. Non-Confidential...
Page 292: B3.1 Error System Register Summary
The ERR0* registers are agnostic to the architectural state. For example, this means that for ERRSELR==0 and ERRSELR_EL1==0, ERXPFGFR and ERXPFGFR_EL1 will both access ERR0PFGFR. For those registers not described in this chapter, see the Arm Architecture Reference Manual Armv8, for ®...
Page 293: B3.2 Err0Addr, Error Record Address Register
PADDR, [39:0] Physical address. Configurations ERR0ADDR resets to UNKNOWN When ERRSELR.SEL==0, this register is accessible from B2.38 ERXADDR_EL1, Selected Error Record Address Register, EL1 on page B2-198. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-293 reserved. Non-Confidential...
Page 294: B3.3 Err0Ctlr, Error Record Control Register
The fault handling interrupt is generated for all detected Deferred errors and Uncorrected errors. The possible values are: Fault handling interrupt disabled. Fault handling interrupt enabled. UI, [2] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-294 reserved. Non-Confidential...
Page 295 Error detection and correction enabled. Configurations This register is accessible from the following registers when ERRSELR.SEL==0: B2.39 ERXCTLR_EL1, Selected Error Record Control Register, EL1 on page B2-199. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-295 reserved. Non-Confidential...
Page 296: B3.4 Err0Fr, Error Record Feature Register
The node implements a control for enabling fault handling interrupts on corrected errors. UE, [9:8] In-band uncorrected error reporting. The value is: The node implements in-band uncorrected error reporting, that is external aborts. FI, [7:6] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-296 reserved. Non-Confidential...
Page 297 The node implements controls for enabling or disabling error detection and correction. Configurations ERR0FR resets to 0x000000000000A9A2 ERR0FR is accessible from the following registers when ERRSELR.SEL==0: B2.40 ERXFR_EL1, Selected Error Record Feature Register, EL1 on page B2-200. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-297 reserved. Non-Confidential...
Page 298: B3.5 Err0Misc0, Error Record Miscellaneous Register 0
Cold reset. If the IMPLEMENTATION DEFINED UNKNOWN reset value is , then the value of this field remains until software initializes it. UNKNOWN UNKNOWN WAY, [31:28] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-298 reserved. Non-Confidential...
Page 299 The encoding is dependent on the unit from which the error being recorded was detected. The possible values are: L2 Cache Indicates which array has the error. The possible values are: L2 Tag RAM. 0b00 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-299 reserved. Non-Confidential...
Page 300 , [31:0] is 0x00000000 UNKNOWN This register is accessible from the following registers when ERRSELR.SEL==0: • B2.41 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1 on page B2-201. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-300 reserved. Non-Confidential...
Page 301: B3.6 Err0Misc1, Error Record Miscellaneous Register 1
B3 Error system registers B3.6 ERR0MISC1, Error Record Miscellaneous Register 1 B3.6 ERR0MISC1, Error Record Miscellaneous Register 1 This register is unused in the Cortex-A76 core and marked as RES0 Configurations When ERRSELR.SEL==0, ERR0MISC1 is accessible from B2.42 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1 on page B2-202.
Page 302: B3.7 Err0Pfgcdnr, Error Pseudo Fault Generation Count Down Register
There are no configuration options. ERR0PFGCDNR resets to UNKNOWN When ERRSELR.SEL==0, ERR0PFGCDNR is accessible from B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1 on page B2-203. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-302 reserved. Non-Confidential...
Page 303: B3.8 Err0Pfgctlr, Error Pseudo Fault Generation Control Register
Deferred Error generation enable. The possible values are: No deferred error is generated. A deferred error might be generated when the Error Generation Counter is triggered. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-303 reserved. Non-Confidential...
Page 304 ERR0PFGCTLR resets to 0x00000000 ERR0PFGCTLR is accessible from the following registers when ERRSELR.SEL==0: • B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1 on page B2-204. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-304 reserved. Non-Confidential...
Page 305: B3.9 Err0Pfgfr, Error Pseudo Fault Generation Feature Register
Signaled or Recoverable Error generation. The value is: The node does not support this feature. UEU, [2] Unrecoverable Error generation. The value is: The node does not support this feature. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-305 reserved. Non-Confidential...
Page 306 There are no configuration notes. ERR0PFGFR resets to 0xC0000062 When ERRSELR.SEL==0, ERR0PFGFR is accessible from B2.45 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1 on page B2-206. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-306 reserved. Non-Confidential...
Page 307: B3.10 Err0Status, Error Record Primary Status Register
Error reported. The possible values are: No external abort has been reported. The node has reported an external abort to the master that is in access or making a transaction. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-307 reserved. Non-Confidential...
Page 308 No errors were deferred. At least one error was not corrected and deferred by poisoning. PN, [22] Poison. The value is: The Cortex-A76 core cannot distinguish a poisoned value from a corrupted value. UET, [21:20] Uncorrected Error Type. The value is: Uncontainable.
Page 309 ERR0STATUS resets to 0x00000000 ERR0STATUS is accessible from the following registers when ERRSELR.SEL==0: • B2.46 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1 on page B2-207. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B3-309 reserved. Non-Confidential...
Page 310 B3 Error system registers B3.10 ERR0STATUS, Error Record Primary Status Register 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. B3-310 Non-Confidential...
Page 311 B4.16 ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1, EL1 on page B4-332. • B4.17 ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1 on page B4-333. • B4.18 AArch64 virtual interface control system register summary on page B4-335. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-311 reserved. Non-Confidential...
Page 312 B4-338. • B4.22 ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register, EL2 on page B4-341. • B4.23 ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2 on page B4-343. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-312 reserved. Non-Confidential...
Page 313: B4.1 Cpu Interface Registers
B4.1 CPU interface registers B4.1 CPU interface registers Each CPU interface block provides the interface for the Cortex-A76 core that interfaces with a GIC distributor within the system. The Cortex-A76 core only supports system register access to the GIC CPU interface registers. The following table lists the three types of GIC CPU interface system registers supported in the Cortex-A76 core.
Page 314: B4.2 Aarch64 Physical Gic Cpu Interface System Register Summary
ICC_SRE_EL2 B4.10 ICC_SRE_EL2, Interrupt Controller System Register Enable register, EL2 on page B4-324 ICC_SRE_EL3 B4.11 ICC_SRE_EL3, Interrupt Controller System Register Enable register, EL3 on page B4-326 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-314 reserved. Non-Confidential...
Page 315 Interrupt active for priority 0x00000002 Interrupt active for priority 0x80000000 0xF8 Details not provided in this description are architecturally defined. See the Arm Generic Interrupt ® Controller Architecture Specification. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-315 reserved.
Page 316 Interrupt active for priority 0x00000002 Interrupt active for priority 0x80000000 0xF8 Details not provided in this description are architecturally defined. See the Arm Generic Interrupt ® Controller Architecture Specification. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-316 reserved.
Page 317: B4.5 Icc_Bpr0_El1, Interrupt Controller Binary Point Register 0, El1
The value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. The minimum value that is implemented is: Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Generic Interrupt Controller Architecture Specification.
Page 318: B4.6 Icc_Bpr1_El1, Interrupt Controller Binary Point Register 1, El1
The minimum value implemented of ICC_BPR1_EL1 Secure register is The minimum value implemented of ICC_BPR1_EL1 Non-secure register is Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Generic Interrupt Controller Architecture Specification.
Page 319: B4.7 Icc_Ctlr_El1, Interrupt Controller Control Register, El1
The core supports 32 levels of physical priority with 5 priority bits. RES0, [7] Reserved, RES0 PMHE, [6] Priority Mask Hint Enable. This bit is read only and is an alias of ICC_CTLR_EL3.PMHE. The possible values are: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-319 reserved. Non-Confidential...
Page 320 ICC_BPR1 determines the preemption group for Group 1 interrupts. ICC_BPR0 determines the preemption group for Group 0 and Group 1 interrupts. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Generic Interrupt Controller Architecture Specification.
Page 321: B4.8 Icc_Ctlr_El3, Interrupt Controller Control Register, El3
The CPU interface logic does not support generation of SEIs. IDbits, [13:11] Identifier bits. The value is: The number of physical interrupt identifier bits supported is 16 bits. This field is an alias of ICC_CTLR_EL3.IDbits. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-321 reserved. Non-Confidential...
Page 322 Control whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupt at EL1. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Generic Interrupt Controller Architecture Specification.
Page 323: B4.9 Icc_Sre_El1, Interrupt Controller System Register Enable Register, El1
This bit is RAO/WI. The core only supports a system register interface to the GIC CPU interface. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Generic Interrupt Controller Architecture Specification.
Page 324: B4.10 Icc_Sre_El2, Interrupt Controller System Register Enable Register, El2
This bit is an alias of ICC_SRE_EL3.DFB SRE, [0] System Register Enable. The value is: The System register interface for the current Security state is enabled. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-324 reserved. Non-Confidential...
Page 325 This bit is RAO/WI. The core only supports a system register interface to the GIC CPU interface. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Generic Interrupt Controller Architecture Specification.
Page 326: B4.11 Icc_Sre_El3, Interrupt Controller System Register Enable Register, El3
Disable FIQ bypass. The possible values are: FIQ bypass enabled. FIQ bypass disabled. SRE, [0] System Register Enable. The value is: The System register interface for the current Security state is enabled. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-326 reserved. Non-Confidential...
Page 327 This bit is RAO/WI. The core only supports a system register interface to the GIC CPU interface. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Generic Interrupt Controller Architecture Specification.
Page 328: B4.12 Aarch64 Virtual Gic Cpu Interface Register Summary
ICV_BPR1_EL1 B4.16 ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1, EL1 on page B4-332 ICV_CTLR_EL1 B4.17 ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1 on page B4-333 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-328 reserved. Non-Confidential...
Page 329 Interrupt active for priority 0x00000002 Interrupt active for priority 0x80000000 0xF8 Details that are not provided in this description are architecturally defined. See the Arm Generic ® Interrupt Controller Architecture Specification. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-329 reserved.
Page 330 Interrupt active for priority 0x00000002 Interrupt active for priority 0x80000000 0xF8 Details that are not provided in this description are architecturally defined. See the Arm Generic ® Interrupt Controller Architecture Specification. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-330 reserved.
Page 331: B4.15 Icv_Bpr0_El1, Interrupt Controller Virtual Binary Point Register 0, El1
The value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. The minimum value that is implemented is: Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Generic Interrupt Controller Architecture Specification.
Page 332: B4.16 Icv_Bpr1_El1, Interrupt Controller Virtual Binary Point Register 1, El1
The minimum value that is implemented of ICV_BPR1_EL1 Secure register is The minimum value that is implemented of ICV_BPR1_EL1 Non-secure register is Bit fields and details that are not provided in this description are architecturally defined. See the Arm ®...
Page 333: B4.17 Icv_Ctlr_El1, Interrupt Controller Virtual Control Register, El1
RES0 VEOImode, [1] Virtual EOI mode. The possible values are: ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide both priority drop and interrupt deactivation functionality. Accesses to ICV_DIR_EL1 are UNPREDICTABLE 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-333 reserved. Non-Confidential...
Page 334 Group 1 interrupts. Reads of ICV_BPR1_EL1 return ICV_BPR0_EL1 plus one, saturated to 111. Writes to ICV_BPR1_EL1 are IGNORED. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Generic Interrupt Controller Architecture Specification.
Page 335: B4.18 Aarch64 Virtual Interface Control System Register Summary
ICH_VTR_EL2 B4.22 ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register, EL2 on page B4-341 ICH_VMCR_EL2 3 B4.23 ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2 on page B4-343 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-335 reserved. Non-Confidential...
Page 336 Interrupt active for priority 0x00000002 Interrupt active for priority 0x80000000 0xF8 Details that are not provided in this description are architecturally defined. See the Arm Generic ® Interrupt Controller Architecture Specification. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-336 reserved.
Page 337 Interrupt active for priority 0x00000002 Interrupt active for priority 0x80000000 0xF8 Details that are not provided in this description are architecturally defined. See the Arm Generic ® Interrupt Controller Architecture Specification. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-337 reserved.
Page 338: B4.21 Ich_Hcr_El2, Interrupt Controller Hyp Control Register, El2
Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 1 interrupts trap to EL2. TALL0, [11] Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 0 interrupts to EL2. The possible values are: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-338 reserved. Non-Confidential...
Page 339 LRENPIE, [2] List Register Entry Not Present Interrupt Enable. The possible values are: Maintenance interrupt disabled. Maintenance interrupt is asserted while the EOIcount field is not 0. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-339 reserved. Non-Confidential...
Page 340 En, [0] Enable. The possible values are: Virtual CPU interface operation disabled. Virtual CPU interface operation enabled. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Generic Interrupt Controller Architecture Specification. 100798_0300_00_en Copyright ©...
Page 341: B4.22 Ich_Vmcr_El2, Interrupt Controller Virtual Machine Control Register, El2
ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide priority drop functionality only. ICV_DIR_EL1 provides interrupt deactivation functionality. This bit is an alias of ICV_CTLR_EL1.EOImode. RES0, [8:5] Reserved, RES0 VCBPR, [4] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-341 reserved. Non-Confidential...
Page 342 Virtual Group 0 interrupt enable. The possible values are: Virtual Group 0 interrupts are disabled. Virtual Group 0 interrupts are enabled. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Generic Interrupt Controller Architecture Specification.
Page 343: B4.23 Ich_Vtr_El2, Interrupt Controller Vgic Type Register, El2
System registers. nV4, [20] Direct injection of virtual interrupts not supported. The value is: The CPU interface logic supports direct injection of virtual interrupts. TDS, [19] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B4-343 reserved. Non-Confidential...
Page 344 The number of implemented List registers, minus one. The core implements 4 list registers. Accesses to ICH_LR_EL2[x] (x>3) in AArch64 are UNDEFINED Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Generic Interrupt Controller Architecture Specification. 100798_0300_00_en Copyright ©...
Page 345 B5.6 MVFR2_EL1, Media and VFP Feature Register 2, EL1 on page B5-355. • B5.7 AArch32 register summary on page B5-357. • B5.8 FPSCR, Floating-Point Status and Control Register on page B5-358. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-345 reserved. Non-Confidential...
Page 346: B5.1 Aarch64 Register Summary
The core has several Advanced SIMD and floating-point system registers in the AArch64 execution state. Each register has a specific purpose, specific usage constraints, configurations, and attributes. The following table gives a summary of the Cortex-A76 core Advanced SIMD and floating-point system registers in the AArch64 execution state.
Page 347: B5.2 Fpcr, Floating-Point Control Register
Round to Nearest (RN) mode. This is the reset value. 0b00 Round towards Plus Infinity (RP) mode. 0b01 Round towards Minus Infinity (RM) mode. 0b10 Round towards Zero (RZ) mode. 0b11 RES0, [21:20] Reserved. RES0 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-347 reserved. Non-Confidential...
Page 348 011 0100 0100 Accessibility This register is accessible as follows: EL2 EL3 EL0 EL1 (NS) (SCR.NS = 1) (SCR.NS = 0) RW RW RW RW RW 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-348 reserved. Non-Confidential...
Page 349: B5.3 Fpsr, Floating-Point Status Register
Inexact cumulative exception bit. This bit is set to 1 to indicate that the Inexact exception has occurred since 0 was last written to this bit. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-349 reserved. Non-Confidential...
Page 350 011 0100 0100 Accessibility This register is accessible as follows: EL2 EL3 EL0 EL1 (NS) (SCR.NS = 1) (SCR.NS = 0) RW RW RW RW RW 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-350 reserved. Non-Confidential...
Page 351: B5.4 Mvfr0_El1, Media And Vfp Feature Register 0, El1
Supported, VFPv3 or greater. See the Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile for more ® information. SIMDReg, [3:0] Indicates support for the Advanced SIMD register bank: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-351 reserved. Non-Confidential...
Page 352 CRn CRm op2 000 0000 0011 Accessibility This register is accessible as follows: EL0 EL1(NS) EL1(S) EL2 EL3 (SCR.NS = 1) EL3(SCR.NS = 0) 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-352 reserved. Non-Confidential...
Page 353: B5.5 Mvfr1_El1, Media And Vfp Feature Register 1, El1
Indicates whether the Advanced SIMD and floating-point unit supports load/store instructions: Implemented. FPDNaN, [7:4] Indicates whether the floating-point hardware implementation supports only the Default NaN mode: Hardware supports propagation of NaN values. FPFtZ, [3:0] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-353 reserved. Non-Confidential...
Page 354 CRn CRm op2 000 0000 0011 Accessibility This register is accessible as follows: EL0 EL1(NS) EL1(S) EL2 EL3 (SCR.NS = 1) EL3(SCR.NS = 0) 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-354 reserved. Non-Confidential...
Page 355: B5.6 Mvfr2_El1, Media And Vfp Feature Register 2, El1
MRS <Xt>, MVFR2_EL1 ; Read MVFR2_EL1 into Xt Register access is encoded as follows: Table B5-6 MVFR2_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0011 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-355 reserved. Non-Confidential...
Page 356 B5.6 MVFR2_EL1, Media and VFP Feature Register 2, EL1 Accessibility This register is accessible as follows: EL0 EL1(NS) EL1(S) EL2 EL3 (SCR.NS = 1) EL3(SCR.NS = 0) 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-356 reserved. Non-Confidential...
Page 357: B5.7 Aarch32 Register Summary
AArch32 register summary The core has one Advanced SIMD and floating-point system registers in the AArch32 execution state. The following table gives a summary of the Cortex-A76 core Advanced SIMD and floating-point system registers in the AArch32 execution state. Table B5-7 AArch32 Advanced SIMD and floating-point system registers...
Page 358: B5.8 Fpscr, Floating-Point Status And Control Register
AHP, [26] Alternative Half-Precision control bit: IEEE half-precision format selected. This is the reset value. Alternative half-precision format selected. DN, [25] Default NaN mode control bit: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-358 reserved. Non-Confidential...
Page 359 Inexact cumulative exception bit. This bit is set to 1 to indicate that the Inexact exception has occurred since 0 was last written to this bit. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-359 reserved. Non-Confidential...
Page 360 Register access is encoded as follows: Table B5-8 FPSCR access encoding spec_reg 0001 Note The Cortex-A76 core implementation does not support the deprecated VFP short vector feature. Attempts to execute the associated VFP data-processing instructions result in an Instruction UNDEFINED exception.
Page 361 B5 Advanced SIMD and floating-point registers B5.8 FPSCR, Floating-Point Status and Control Register fields allow access at which Exception levels, see the Arm Architecture Reference Manual Armv8, for ® Armv8-A architecture profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights B5-361 reserved.
Page 362 B5 Advanced SIMD and floating-point registers B5.8 FPSCR, Floating-Point Status and Control Register 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. B5-362 Non-Confidential...
Page 363 Part C Debug descriptions...
Page 365: C1.1 About Debug Methods
Chapter C1 Debug This chapter describes the Cortex-A76 core debug registers and shows examples of how to use them. It contains the following sections: • C1.1 About debug methods on page C1-366. • C1.2 Debug register interfaces on page C1-367.
Page 366 • Restart the core. For self-hosted debug, the debug target runs additional debug monitor software that runs on the Cortex-A76 core itself. This way, it does not require expensive interface hardware to connect a second host computer. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C1-366 reserved.
Page 367: C1.2 Debug Register Interfaces
Software running on the core. • An external debugger. The Cortex-A76 core implements the Armv8 Debug architecture and debug events as described in the Architecture Reference Manual Armv8, for Armv8-A architecture profile. It also implements ® improvements to Debug introduced in Armv8.1 and Armv8.2.
Page 368 Stop at the first column a condition is true, the entry gives the access permission of the register and scanning stops. Table C1-2 External register condition code example Off DLK OSLK EDAD Default 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C1-368 reserved. Non-Confidential...
Page 369: C1.3 Debug Events
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more ® information about the debug events. C1.3.1 Watchpoint debug events In the Cortex-A76 core, watchpoint debug events are always synchronous. Memory hint instructions and cache clean operations, except , do not generate DC ZVA DC IVAC watchpoint debug events.
Page 370 External debug interface For information about external debug interface, including debug memory map and debug signals, see the DynamIQ Shared Unit Technical Reference Manual. ® ™ 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C1-370 reserved. Non-Confidential...
Page 371 C2.2 PMU functional description on page C2-373. • C2.3 PMU events on page C2-374. • C2.4 PMU interrupts on page C2-383. • C2.5 Exporting PMU events on page C2-384. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C2-371 reserved. Non-Confidential...
Page 372: C2.1 About The Pmu
C2.1 About the PMU The Cortex-A76 core includes performance monitors that enable you to gather various statistics on the operation of the core and its memory system during runtime. These provide useful information about the behavior of the core that you can use when debugging or profiling code.
Page 373: C2.2 Pmu Functional Description
The PMU has 32-bit counters that increment when they are enabled, based on events, and a 64- bit cycle counter. PMU register interfaces The Cortex-A76 core supports access to the performance monitor registers from the internal system register interface and a memory-mapped interface. C2.2.1...
Page 374: C2.3 Pmu Events
The following instructions are not counted: • Cache maintenance instructions and prefetches. • Non-cacheable accesses. This event counts the sum of L1D_CACHE_RD and L1D_CACHE_WR. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C2-374 reserved. Non-Confidential...
Page 375 This event counts any instruction fetch which accesses the L1 instruction cache or L0 Macro-op cache. The following instructions are not counted: • Cache maintenance instructions. • Non-cacheable accesses. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C2-375 reserved. Non-Confidential...
Page 376 0x1E [39] CHAIN For odd-numbered counters, increments the count by one for each overflow of the preceding even-numbered counter. For even-numbered counters, there is no increment. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C2-376 reserved. Non-Confidential...
Page 377 Attributable L2 data or unified TLB refill. This event counts on any refill of the L2 TLB, caused by either an instruction or data access. This event does not count if the MMU is disabled. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C2-377 reserved. Non-Confidential...
Page 378 L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL_WR event causes this event to count. The following instructions are not counted: • Cache maintenance instructions and prefetches. • Non-cacheable accesses. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C2-378 reserved. Non-Confidential...
Page 379 L1 which looks up in the L2 cache or any write-back from L1 which allocates into the L2 cache. Snoops from outside the core are not counted. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C2-379 reserved. Non-Confidential...
Page 380 • Cache maintenance instructions. • Translation table walks. • Prefetches. 0x68 [97:96] UNALIGNED_LD_SPEC Unaligned access, read 0x69 [99:98] UNALIGNED_ST_SPEC Unaligned access, write 0x6A [102:100] UNALIGNED_LDST_SPEC Unaligned access 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C2-380 reserved. Non-Confidential...
Page 381 [148] EXC_TRAP_IRQ Exception taken, IRQ not taken locally. 0x8F [149] EXC_TRAP_FIQ Exception taken, FIQ not taken locally. 0x90 [152:150] RC_LD_SPEC Release consistency operation speculatively executed, load-acquire. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C2-381 reserved. Non-Confidential...
Page 382 (continued) Event Event mnemonic Event description number event bus (to trace) 0x91 [155:153] RC_ST_SPEC Release consistency operation speculatively executed, store-release. 0xA0 [166] L3_CACHE_RD L3 cache read. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C2-382 reserved. Non-Confidential...
Page 383: C2.4 Pmu Interrupts
You can route this signal to an external interrupt controller for prioritization and masking. This is the only mechanism that signals this interrupt to the core. This interrupt is also driven as a trigger input to the CTI. See the Arm DynamIQ Shared Unit Technical ®...
Page 384: C2.5 Exporting Pmu Events
The PMUEVENT bus is not exported to external components. This is because the event bus cannot safely cross an asynchronous boundary when events can be generated on every cycle. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C2-384 reserved.
Page 385 C3.1 About the AMU on page C3-386. • C3.2 Accessing the activity monitors on page C3-387. • C3.3 AMU counters on page C3-388. • C3.4 AMU events on page C3-389. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C3-385 reserved. Non-Confidential...
Page 386: C3.1 About The Amu
The activity monitors provide useful information for system power management and persistent monitoring. The activity monitors are read-only in operation and their configuration is limited to the highest Exception level implemented. The Cortex-A76 core implements five counters, 0-4, and activity monitoring is only implemented in AArch64. 100798_0300_00_en Copyright ©...
Page 387: C3.2 Accessing The Activity Monitors
Access enable bit The access enable bit for traps on accesses to activity monitor registers is required at EL2 and EL3. In the Cortex-A76 core, the CPUAMEN[4] bit in registers ACTLR_EL2 and ACTLR_EL3 controls the activity monitor registers enable. Note In the Cortex-A76 core, the CPUAMEN[4] bit is in ACTLR (S) and HACTLR.
Page 388: C3.3 Amu Counters
C3.3 AMU counters C3.3 AMU counters The Cortex-A76 core implements five counters, 0-4. The activity monitor counters, CPUAMEVCNTR0-4, have the following characteristics: • All events are counted in 64-bit wrapping counters that overflow when they wrap. There is no support for overflow status indication or interrupts.
Page 389: C3.4 Amu Events
C3 Activity Monitor Unit C3.4 AMU events C3.4 AMU events The following table describes the counters that are implemented in the Cortex-A76 core and the mapping to fixed and programmable events. Table C3-1 Mapping of counters to fixed events Activity...
Page 391 Chapter C4 Embedded Trace Macrocell This chapter describes the ETM for the Cortex-A76 core. It contains the following sections: • C4.1 About the ETM on page C4-392. • C4.2 ETM trace unit generation options and resources on page C4-393. •...
Page 392: C4.1 About The Etm
About the ETM The ETM trace unit is a module that performs real-time instruction flow tracing based on the ETMv4 architecture. The ETM is a CoreSight component, and is an integral part of the Arm Real-time Debug solution, DS-5 Development Studio.
Page 393: C4.2 Etm Trace Unit Generation Options And Resources
Number of resource selection pairs implemented Number of external input selectors implemented Number of external inputs implemented 165, 4 CTI + 161 PMU Number of counters implemented 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C4-393 reserved. Non-Confidential...
Page 394 Number of address comparator pairs implemented Number of single-shot comparator controls Number of core comparator inputs implemented Data address comparisons implemented Not implemented Number of data value comparators implemented 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C4-394 reserved. Non-Confidential...
Page 395: C4.3 Etm Trace Unit Functional Description
The trace generation logic does not generate any new trace until the FIFO is emptied. This causes a gap in the trace when viewed in the debugger. Trace out Trace from FIFO is output on the AMBA ATB interface. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C4-395 reserved. Non-Confidential...
Page 396: C4.4 Resetting The Etm
If the ETM trace unit is reset, tracing stops until the ETM trace unit is reprogrammed and re-enabled. However, if the core is reset using Warm reset, the last few instructions provided by the core before the reset might not be traced. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C4-396 reserved. Non-Confidential...
Page 397: C4.5 Programming And Reading Etm Trace Unit Registers
Program all trace registers required Set main enable bit in TRCPRGCTLR to 0b1 Read TRCSTATR Is TRCSTATR Idle 0b0? Figure C4-2 Programming ETM trace unit registers 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights C4-397 reserved. Non-Confidential...
Page 398: C4.6 Etm Trace Unit Register Interfaces
C4 Embedded Trace Macrocell C4.6 ETM trace unit register interfaces C4.6 ETM trace unit register interfaces The Cortex-A76 core supports only memory-mapped interface to trace registers. See the Arm Embedded Trace Macrocell Architecture Specification ETMv4 for information on the ®...
Page 399: C4.7 Interaction With The Pmu And Debug
This section describes the interaction with the PMU and the effect of debug double lock on trace register access. Interaction with the PMU The Cortex-A76 core includes a PMU that enables events, such as cache misses and instructions executed, to be counted over a period of time. The PMU and ETM trace unit function together.
Page 401 Part D Debug registers...
Page 403: D1.1 Aarch32 Debug Register Summary
This chapter describes the debug registers in the AArch32 Execution state and shows examples of how to use them. It contains the following section: • D1.1 AArch32 debug register summary on page D1-404. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D1-403 reserved. Non-Confidential...
Page 404 CRn, op2, CRm, Op1 or instructions in the order of CRm, MCRR MRRC Op1. For those registers not described in this chapter, see the Arm Architecture Reference Manual Arm v8, for ® ® v8-A architecture profile.
Page 405: D2.1 Aarch64 Debug Register Summary
D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1 on page D2-408. • D2.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1 on page D2-411. • D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1 on page D2-412. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D2-405 reserved. Non-Confidential...
Page 406 D3.1 Memory-mapped debug register summary on page D3-416 for a complete list of registers accessible from the external debug interface. The 64-bit registers cover two addresses on the external memory interface. For those registers not described in this chapter, see the Arm Architecture Reference ®...
Page 407: D2.2 Dbgbcrn_El1, Debug Breakpoint Control Registers, El1
D2.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1 on page D2-411 0x00000000 32 DBGCLAIMCLR_EL1 Debug Claim Tag Clear Register 0x000000AA 32 DBGAUTHSTATUS_EL1 RO Debug Authentication Status Register 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D2-407 reserved. Non-Confidential...
Page 408 Match address. DBGBVRn_EL1 is the address of an instruction. 0b000 Match context ID. DBGBVRn_EL1[31:0] is a context ID. 0b001 Match VMID. DBGBVRn_EL1[47:32] is a VMID. 0b010 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D2-408 reserved. Non-Confidential...
Page 409 See the Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile for more ® information on how the BAS field is interpreted by hardware. RES0, [4:3] Reserved. RES0 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D2-409 reserved. Non-Confidential...
Page 410 A debugger must ensure that UNKNOWN DBGBCRn_EL1.E has a defined value before it enables debug. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 411 CLAIM bits. A single write operation can set multiple bits to 1. Writing 0 to one of these bits has no effect. Bit fields and details not provided in this description are architecturally defined. See the Arm ®...
Page 412 This field must be interpreted along with the HMC and PAC fields. On Cold reset, the field reset value is architecturally UNKNOWN 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D2-412 reserved. Non-Confidential...
Page 413 Watchpoint disabled. Watchpoint enabled. On Cold reset, the field reset value is architecturally UNKNOWN Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D2-413 reserved.
Page 414 D2 AArch64 debug registers D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. D2-414 Non-Confidential...
Page 415 D3.12 EDPIDR4, External Debug Peripheral Identification Register 4 on page D3-430. • D3.13 EDPIDRn, External Debug Peripheral Identification Registers 5-7 on page D3-431. • D3.14 EDRCR, External Debug Reserve Control Register on page D3-432. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D3-415 reserved. Non-Confidential...
Page 416: D3.1 Memory-Mapped Debug Register Summary
Memory-mapped debug register summary The following table shows the offset address for the registers that are accessible from the external debug interface. For those registers not described in this chapter, see the Arm Architecture Reference Manual Armv8, for ® Armv8-A architecture profile.
Page 417 D2-412 0x80C Reserved 0x810 DBGWVR1_EL1[31:0] Debug Watchpoint Value Register 1 0x814 DBGWVR1_EL1[63:32] 0x818 DBGWCR1_EL1 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1 on page D2-412 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D3-417 reserved. Non-Confidential...
Page 418 D3.6 EDDEVID, External Debug Device ID Register 0 on page D3-424 0xFCC EDDEVTYPE External Debug Device Type Register 0xFD0 EDPIDR4 D3.12 EDPIDR4, External Debug Peripheral Identification Register 4 on page D3-430 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D3-418 reserved. Non-Confidential...
Page 419 0xFF8 EDCIDR2 D3.4 EDCIDR2, External Debug Component Identification Register 2 on page D3-422 0xFFC EDCIDR3 D3.5 EDCIDR3, External Debug Component Identification Register 3 on page D3-423 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D3-419 reserved. Non-Confidential...
Page 420: D3.2 Edcidr0, External Debug Component Identification Register 0
PRMBL_0, [7:0] Preamble byte 0. 0x0D Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The EDCIDR0 can be accessed through the external debug interface, offset...
Page 421: D3.3 Edcidr1, External Debug Component Identification Register 1
Debug component. PRMBL_1, [3:0] Preamble. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The EDCIDR1 can be accessed through the external debug interface, offset...
Page 422: D3.4 Edcidr2, External Debug Component Identification Register 2
PRMBL_2, [7:0] Preamble byte 2. 0x05 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The EDCIDR2 can be accessed through the external debug interface, offset...
Page 423: D3.5 Edcidr3, External Debug Component Identification Register 3
PRMBL_3, [7:0] Preamble byte 3. 0xB1 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The EDCIDR3 can be accessed through the external debug interface, offset...
Page 424: D3.6 Eddevid, External Debug Device Id Register 0
None supported. RES0, [23:0] Reserved. RES0 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The EDDEVID can be accessed through the external debug interface, offset...
Page 425: D3.7 Eddevid1, External Debug Device Id Register 1
Figure D3-6 EDDEVID1 bit assignments RES0, [31:0] Reserved. RES0 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The EDDEVID1 can be accessed through the external debug interface, offset...
Page 426: D3.8 Edpidr0, External Debug Peripheral Identification Register 0
Part_0, [7:0] Least significant byte of the debug part number. 0x0B Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The EDPIDR0 can be accessed through the external debug interface, offset...
Page 427: D3.9 Edpidr1, External Debug Peripheral Identification Register 1
Arm Limited. This is the least significant nibble of JEP106 ID code. Part_1, [3:0] Most significant nibble of the debug part number. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 428: D3.10 Edpidr2, External Debug Peripheral Identification Register 2
DES_1, [2:0] Arm Limited. This is the most significant nibble of JEP106 ID code. 0b011 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The EDPIDR2 can be accessed through the external debug interface, offset...
Page 429: D3.11 Edpidr3, External Debug Peripheral Identification Register 3
Part minor revision. CMOD, [3:0] Customer modified. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The EDPIDR3 can be accessed through the external debug interface, offset...
Page 430: D3.12 Edpidr4, External Debug Peripheral Identification Register 4
ID registers. DES_2, [3:0] Arm Limited This is the least significant nibble JEP106 continuation code. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 431: D3.13 Edpidrn, External Debug Peripheral Identification Registers 5-7
EDPIDRn, External Debug Peripheral Identification Registers 5-7 No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are RES0 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D3-431 reserved. Non-Confidential...
Page 432: D3.14 Edrcr, External Debug Reserve Control Register
0x090 Usage constraints This register is accessible as follows: DLK OSLK SLK Default Error Error Error Configurations EDRCR is in the Core power domain. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D3-432 reserved. Non-Confidential...
Page 433 D4.2 PMCEID0, Performance Monitors Common Event Identification Register 0 on page D4-436. • D4.3 PMCEID1, Performance Monitors Common Event Identification Register 1 on page D4-439. • D4.4 PMCR, Performance Monitors Control Register on page D4-441. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D4-433 reserved. Non-Confidential...
Page 434: D4.1 Aarch32 Pmu Register Summary
64-bit registers. MCRR MRRC The following table gives a summary of the Cortex-A76 PMU registers in the AArch32 Execution state. For those registers not described in this chapter, see the Arm Architecture Reference Manual Armv8, for ® Armv8-A architecture profile.
Page 435 CRn Op1 CRm Op2 Name Type Width Reset Description PMEVTYPER0 Performance Monitors Event Type Registers PMEVTYPER1 PMEVTYPER2 PMEVTYPER3 PMEVTYPER4 PMEVTYPER5 PMCCFILTR Performance Monitors Cycle Count Filter Register 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D4-435 reserved. Non-Confidential...
Page 436: D4.2 Pmceid0, Performance Monitors Common Event Identification Register 0
Common architectural and microarchitectural feature events that can be counted by the PMU event counters. The following table shows the PMCEID0 bit assignments with event implemented or not implemented when the associated bit is set to 1 or 0. See the Arm Architecture Reference ®...
Page 437 Instruction architecturally executed, condition check pass - write to CONTEXTIDR: This event is implemented. [10] EXC_RETURN Instruction architecturally executed, condition check pass - exception return: This event is implemented. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D4-437 reserved. Non-Confidential...
Page 438 This event counts any instruction fetch which misses in the cache. The … on page C2-374. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 439: D4.3 Pmceid1, Performance Monitors Common Event Identification Register 1
This event is implemented. STALL_FRONTEND No operation issued due to frontend. This event is implemented. BR_MIS_PRED_RETIRED Instruction architecturally executed, mispredicted branch. This event is not implemented. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D4-439 reserved. Non-Confidential...
Page 440 This event counts any instruction fetch which misses in the cache. The … on page C2-374. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 441: D4.4 Pmcr, Performance Monitors Control Register
Cycle counter operates regardless of the non-invasive debug authentication settings. This is the reset value. Cycle counter is disabled if non-invasive debug is not permitted and enabled. X, [4] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D4-441 reserved. Non-Confidential...
Page 442 No action. This is the reset value. Reset PMCCNTR to zero. This bit is always RAZ. Resetting PMCCNTR does not clear the PMCCNTR overflow bit to 0. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.
Page 443 On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch32. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally values. UNKNOWN 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D4-443 reserved. Non-Confidential...
Page 444 D4 AArch32 PMU registers D4.4 PMCR, Performance Monitors Control Register 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. D4-444 Non-Confidential...
Page 445: D5.1 Aarch64 Pmu Register Summary
D5-448. • D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0 on page D5-451. • D5.4 PMCR_EL0, Performance Monitors Control Register, EL0 on page D5-453. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D5-445 reserved. Non-Confidential...
Page 446 The PMU counters and their associated control registers are accessible in the AArch64 Execution state with instructions. The following table gives a summary of the Cortex-A76 PMU registers in the AArch64 Execution state. For those registers not described in this chapter, see the Arm Architecture Reference Manual Armv8, for ® Armv8-A architecture profile.
Page 447 PMEVTYPER0_EL0 Performance Monitors Event Type Registers PMEVTYPER1_EL0 PMEVTYPER2_EL0 PMEVTYPER3_EL0 PMEVTYPER4_EL0 PMEVTYPER5_EL0 PMCCFILTR_EL0 Performance Monitors Cycle Count Filter Register Related references C2.3 PMU events on page C2-374 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D5-447 reserved. Non-Confidential...
Page 448 [26] MEMORY_ERROR Local memory error: This event is implemented. [25] BUS_ACCESS Bus access: This event is implemented. [24] L2D_CACHE_WB L2 Data cache Write-Back: This event is implemented. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D5-448 reserved. Non-Confidential...
Page 449 Instruction architecturally executed, condition check pass - write to CONTEXTIDR: This event is implemented. [10] EXC_RETURN Instruction architecturally executed, condition check pass - exception return: This event is implemented. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D5-449 reserved. Non-Confidential...
Page 450 (condition code check pass). 0x1 [01] L1I_CACHE_REFILL L1 instruction cache refill. This event counts any instruction fetch which misses in the cache. The … on page C2-374. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D5-450 reserved. Non-Confidential...
Page 451 This event is implemented. STALL_FRONTEND No operation issued due to frontend. This event is implemented. BR_MIS_PRED_RETIRED Instruction architecturally executed, mispredicted branch. This event is not implemented. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D5-451 reserved. Non-Confidential...
Page 452 (condition code check pass). 0x1 [01] L1I_CACHE_REFILL L1 instruction cache refill. This event counts any instruction fetch which misses in the cache. The … on page C2-374. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D5-452 reserved. Non-Confidential...
Page 453 This bit is read/write. X, [4] Export enable. This bit permits events to be exported to another debug device, such as a trace macrocell, over an event bus: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D5-453 reserved. Non-Confidential...
Page 454 Configurations AArch64 System register PMCR_EL0 is architecturally mapped to AArch32 System register PMCR. Bit fields and details that are not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. 100798_0300_00_en Copyright ©...
Page 455 D6.10 PMPIDR3, Performance Monitors Peripheral Identification Register 3 on page D6-468. • D6.11 PMPIDR4, Performance Monitors Peripheral Identification Register 4 on page D6-469. • D6.12 PMPIDRn, Performance Monitors Peripheral Identification Register 5-7 on page D6-470. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D6-455 reserved. Non-Confidential...
Page 456: D6.1 Memory-Mapped Pmu Register Summary
PMVIDSR VMID Sample Register 0x220 PMPCSR[31:0] Program Counter Sample Register (alias) 0x224 PMPCSR[63:32] 0x228 PMCID1SR CONTEXTIDR_EL1 Sample Register (alias) 0x22C PMCID2SR CONTEXTIDR_EL2 Sample Register 0x100-0x3FC Reserved 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D6-456 reserved. Non-Confidential...
Page 457 PMINTENCLR_EL1 Performance Monitor Interrupt Enable Clear Register 0xC64-0xC7C Reserved 0xC80 PMOVSCLR_EL0 Performance Monitor Overflow Flag Status Register 0xC84-0xC9C Reserved 0xCA0 PMSWINC_EL0 Performance Monitor Software Increment Register 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D6-457 reserved. Non-Confidential...
Page 458 D6.12 PMPIDRn, Performance Monitors Peripheral Identification Register 5-7 0xFD8 PMPIDR6 on page D6-470 0xFDC PMPIDR7 0xFE0 PMPIDR0 D6.7 PMPIDR0, Performance Monitors Peripheral Identification Register 0 on page D6-465 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D6-458 reserved. Non-Confidential...
Page 459 0xFF8 PMCIDR2 D6.5 PMCIDR2, Performance Monitors Component Identification Register 2 on page D6-463 0xFFC PMCIDR3 D6.6 PMCIDR3, Performance Monitors Component Identification Register 3 on page D6-464 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D6-459 reserved. Non-Confidential...
Page 460: D6.2 Pmcfgr, Performance Monitors Configuration Register
Number of event counters. The value is: Six counters. 0x06 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The PMCFGR can be accessed through the external debug interface, offset...
Page 461: D6.3 Pmcidr0, Performance Monitors Component Identification Register 0
PRMBL_0, [7:0] Preamble byte 0. 0x0D Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The PMCIDR0 can be accessed through the external debug interface, offset...
Page 462: D6.4 Pmcidr1, Performance Monitors Component Identification Register 1
Debug component. PRMBL_1, [3:0] Preamble byte 1. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The PMCIDR1 can be accessed through the external debug interface, offset...
Page 463: D6.5 Pmcidr2, Performance Monitors Component Identification Register 2
PRMBL_2, [7:0] Preamble byte 2. 0x05 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The PMCIDR2 can be accessed through the external debug interface, offset...
Page 464: D6.6 Pmcidr3, Performance Monitors Component Identification Register 3
PRMBL_3, [7:0] Preamble byte 3. 0xB1 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The PMCIDR3 can be accessed through the external debug interface, offset...
Page 465: D6.7 Pmpidr0, Performance Monitors Peripheral Identification Register 0
Part_0, [7:0] Least significant byte of the performance monitor part number. 0x0B Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The PMPIDR0 can be accessed through the external debug interface, offset...
Page 466: D6.8 Pmpidr1, Performance Monitors Peripheral Identification Register 1
Arm Limited. This is the least significant nibble of JEP106 ID code. Part_1, [3:0] Most significant nibble of the performance monitor part number. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 467: D6.9 Pmpidr2, Performance Monitors Peripheral Identification Register 2
DES_1, [2:0] Arm Limited. This is the most significant nibble of JEP106 ID code. 0b011 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The PMPIDR2 can be accessed through the external debug interface, offset...
Page 468: D6.10 Pmpidr3, Performance Monitors Peripheral Identification Register 3
Part minor revision. CMOD, [3:0] Customer modified. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The PMPIDR3 can be accessed through the external debug interface, offset...
Page 469: D6.11 Pmpidr4, Performance Monitors Peripheral Identification Register 4
ID registers. DES_2, [3:0] Arm Limited. This is the least significant nibble JEP106 continuation code. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 470: D6.12 Pmpidrn, Performance Monitors Peripheral Identification Register 5-7
PMPIDRn, Performance Monitors Peripheral Identification Register 5-7 No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are RES0 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D6-470 reserved. Non-Confidential...
Page 471 D7.7 PMCCNTSR, PMU Cycle Counter Snapshot Register on page D7-478. • D7.8 PMEVCNTSRn, PMU Cycle Counter Snapshot Registers 0-5 on page D7-479. • D7.9 PMSSCR, PMU Snapshot Capture Register on page D7-480. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D7-471 reserved. Non-Confidential...
Page 472: D7.1 Pmu Snapshot Register Summary
0x620 + 4×n PMEVCNTSRn D7.8 PMEVCNTSRn, PMU Cycle Counter Snapshot Registers 0-5 on page D7-479 0x6F0 PMSSCR D7.9 PMSSCR, PMU Snapshot Capture Register on page D7-480 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D7-472 reserved. Non-Confidential...
Page 473: D7.2 Pmpcssr, Snapshot Program Counter Sample Register
Usage constraints Any access to PMPCSSR returns an error if any of the following occurs: • The core power domain is off. • DoubleLockStatus() == TRUE. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D7-473 reserved. Non-Confidential...
Page 474: D7.3 Pmcidssr, Snapshot Contextidr_El1 Sample Register
Usage constraints Any access to PMCIDSSR returns an error if any of the following occurs: • The core power domain is off. • DoubleLockStatus() == TRUE. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D7-474 reserved. Non-Confidential...
Page 475: D7.4 Pmcid2Ssr, Snapshot Contextidr_El2 Sample Register
Usage constraints Any access to PMCID2SSR returns an error if any of the following occurs: • The core power domain is off. • DoubleLockStatus() == TRUE. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D7-475 reserved. Non-Confidential...
Page 476: D7.5 Pmsssr, Pmu Snapshot Status Register
Usage constraints Any access to PMSSSR returns an error if any of the following occurs: • The core power domain is off. • DoubleLockStatus() == TRUE. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D7-476 reserved. Non-Confidential...
Page 477: D7.6 Pmovssr, Pmu Overflow Status Snapshot Register
Usage constraints Any access to PMOVSSR returns an error if any of the following occurs: • The core power domain is off. • DoubleLockStatus() == TRUE. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D7-477 reserved. Non-Confidential...
Page 478: D7.7 Pmccntsr, Pmu Cycle Counter Snapshot Register
Usage constraints Any access to PMCCNTSR returns an error if any of the following occurs: • The core power domain is off. • DoubleLockStatus() == TRUE. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D7-478 reserved. Non-Confidential...
Page 479: D7.8 Pmevcntsrn, Pmu Cycle Counter Snapshot Registers 0-5
Usage constraints Any access to PMSSEVCNTRn returns an error if any of the following occurs: • The core power domain is off. • DoubleLockStatus() == TRUE. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D7-479 reserved. Non-Confidential...
Page 480: D7.9 Pmsscr, Pmu Snapshot Capture Register
Usage constraints Any access to PMSSCR returns an error if any of the following occurs: • The core power domain is off. • DoubleLockStatus() == TRUE. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D7-480 reserved. Non-Confidential...
Page 481 D8.5 AMUSERENR_EL0, Activity Monitor EL0 Enable access, EL0 on page D8-487. • D8.6 AMEVCNTRn_EL0, Activity Monitor Event Counter Register, EL0 on page D8-489. • D8.7 AMEVTYPERn_EL0, Activity Monitor Event Type Register, EL0 on page D8-490. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D8-481 reserved. Non-Confidential...
Page 482: D8.1 Aarch64 Amu Register Summary
Register, EL0 on page D8-490 • AMEVTYPER0_EL0 = 0x00000011. • AMEVTYPER1_EL0 = 0x000000EF. • AMEVTYPER2_EL0 = 0x00000008. • AMEVTYPER3_EL0 = 0x000000F0. • AMEVTYPER4_EL0 = 0x000000F1. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D8-482 reserved. Non-Confidential...
Page 483: D8.2 Amcntenclr0_El0, Activity Monitors Count Enable Clear Register, El0
If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped to EL3. If AMUSERENR_EL0.EN is 0, then accesses to this register from EL0 are trapped to EL1. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D8-483 reserved. Non-Confidential...
Page 484: D8.3 Amcntenset_El0, Activity Monitors Count Enable Set Register, El0
If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped to EL3. If AMUSERENR_EL0.EN is 0, then accesses to this register from EL0 are trapped to EL1. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D8-484 reserved. Non-Confidential...
Page 485: D8.4 Amcfgr_El0, Activity Monitors Configuration Register, El0
Armv8-A architecture, the largest counter has 64 bits, therefore the value of this field is 0b111111 N, [7:0] Number of activity counters implemented, where the number of counters is N+1. The Cortex-A76 core implements five counters, therefore the value is 0x04 Configurations There are no configuration notes.
Page 486 If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped to EL3. If AMUSERENR_EL0.EN is 0, then accesses to this register from EL0 are trapped to EL1. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D8-486 reserved. Non-Confidential...
Page 487: D8.5 Amuserenr_El0, Activity Monitor El0 Enable Access, El0
This register is accessible as follows: EL0 EL1 EL2 EL3 RW RW RW Note AMUSERENR_EL0 is always RO at EL0 and not trapped by the EN bit. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D8-487 reserved. Non-Confidential...
Page 488 If ACTLR_EL2.AMEN is 0, then Non-secure accesses to this register from EL0 and EL1 are trapped to EL2. If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped to EL3. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D8-488 reserved. Non-Confidential...
Page 489: D8.6 Amevcntrn_El0, Activity Monitor Event Counter Register, El0
If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped to EL3. If AMUSERENR_EL0.EN is 0, then accesses to this register from EL0 are trapped to EL1. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D8-489 reserved. Non-Confidential...
Page 490: D8.7 Amevtypern_El0, Activity Monitor Event Type Register, El0
This register can also be accessed through the external memory-mapped interface, offset . In this case, it is read-only. 0x400+4n This register is accessible as follows: EL0 EL1 EL2 EL3 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D8-490 reserved. Non-Confidential...
Page 491 If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped to EL3. If AMUSERENR_EL0.EN is 0, then accesses to this register from EL0 are trapped to EL1. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D8-491 reserved. Non-Confidential...
Page 492 D8 AArch64 AMU registers D8.7 AMEVTYPERn_EL0, Activity Monitor Event Type Register, EL0 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. D8-492 Non-Confidential...
Page 493 D9.21 TRCDEVAFF0, Device Affinity Register 0 on page D9-524. • D9.22 TRCDEVAFF1, Device Affinity Register 1 on page D9-526. • D9.23 TRCDEVARCH, Device Architecture Register on page D9-527. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-493 reserved. Non-Confidential...
Page 494 D9.74 TRCVISSCTLR, ViewInst Start-Stop Control Register on page D9-586. • D9.75 TRCVMIDCVR0, VMID Comparator Value Register 0 on page D9-587. • D9.76 TRCVMIDCCTLR0, Virtual context identifier Comparator Control Register 0 on page D9-588. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-494 reserved. Non-Confidential...
Page 495: D9.1 Etm Register Summary
D9.64 TRCSEQSTR, Sequencer State Register on page D9-575 0x120 TRCEXTINSELR D9.28 TRCEXTINSELR, External Input Select Register on page D9-533 0x140 TRCCNTRLDVR0 D9.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1 on page D9-519 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-495 reserved. Non-Confidential...
Page 496 D9.52 TRCPDCR, Power Down Control Register on page D9-562 0x314 0x00000023 TRCPDSR D9.53 TRCPDSR, Power Down Status Register on page D9-563 0x400 TRCACVRn D9.3 TRCACVRn, Address Comparator Value Registers 0-7 on page D9-501 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-496 reserved. Non-Confidential...
Page 497 0xFE8 TRCPIDR2 D9.56 TRCPIDR2, ETM Peripheral Identification Register 2 0x0000000B on page D9-566 0xFEC TRCPIDR3 D9.57 TRCPIDR3, ETM Peripheral Identification Register 3 0x00000000 on page D9-567 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-497 reserved. Non-Confidential...
Page 498 0xFF8 TRCCIDR2 D9.12 TRCCIDR2, ETM Component Identification Register 2 0x00000005 on page D9-511 0xFFC TRCCIDR3 D9.13 TRCCIDR3, ETM Component Identification Register 3 0x000000B1 on page D9-512 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-498 reserved. Non-Confidential...
Page 499: D9.2 Trcacatrn, Address Comparator Access Type Registers 0-7
Bit[11] Exception level 3. RES0, [7:4] Reserved. RES0 CONTEXT TYPE, [3:2] Controls whether the trace unit performs a Context ID comparison, a VMID comparison, or both comparisons: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-499 reserved. Non-Confidential...
Page 500 Type of comparison: Instruction address, 0b00 RES0 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCACATRn can be accessed through the external debug interface, offset...
Page 501: D9.3 Trcacvrn, Address Comparator Value Registers 0-7
Figure D9-2 TRCACVRn bit assignments ADDRESS, [63:0] The address value to compare against. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCACVRn can be accessed through the external debug interface, offset...
Page 502: D9.4 Trcauthstatus, Authentication Status Register
Non-secure Invasive Debug: Non-secure Invasive Debug is not implemented. 0b00 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCAUTHSTATUS can be accessed through the external debug interface, offset...
Page 503: D9.5 Trcauxctlr, Auxiliary Control Register
Override TS packet insertion behavior. The possible values are: Timestamp packets are inserted into FIFO only when trace activity is LOW. Timestamp packets are inserted into FIFO irrespective of trace activity. SYNCOVERRIDE, [3] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-503 reserved. Non-Confidential...
Page 504 When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior. The TRCAUXCTLR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x018 Configurations Available in all configurations. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-504 reserved. Non-Confidential...
Page 505: D9.6 Trcbbctlr, Branch Broadcast Control Register
The address range that address range comparator pair defines, is selected. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCBBCTLR can be accessed through the external debug interface, offset...
Page 506: D9.7 Trcccctlr, Cycle Count Control Register
RES0 THRESHOLD, [11:0] Instruction trace cycle count threshold. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCCCCTLR can be accessed through the external debug interface, offset...
Page 507: D9.8 Trccidcctlr0, Context Id Comparator Control Register 0
The trace unit ignores the relevant byte in TRCCIDCVR0 when it performs the Context ID comparison. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 508: D9.9 Trccidcvr0, Context Id Comparator Value Register 0
RES0 VALUE, [31:0] The data value to compare against. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCCIDCVR0 can be accessed through the external debug interface, offset...
Page 509: D9.10 Trccidr0, Etm Component Identification Register 0
PRMBL_0, [7:0] Preamble byte 0. 0x0D Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCCIDR0 can be accessed through the external debug interface, offset...
Page 510: D9.11 Trccidr1, Etm Component Identification Register 1
Debug component. PRMBL_1, [3:0] Preamble byte 1. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCCIDR1 can be accessed through the external debug interface, offset...
Page 511: D9.12 Trccidr2, Etm Component Identification Register 2
PRMBL_2, [7:0] Preamble byte 2. 0x05 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCCIDR2 can be accessed through the external debug interface, offset...
Page 512: D9.13 Trccidr3, Etm Component Identification Register 3
PRMBL_3, [7:0] Preamble byte 3. 0xB1 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCCIDR3 can be accessed through the external debug interface, offset...
Page 513: D9.14 Trcclaimclr, Claim Tag Clear Register
On writes, for each bit: Has no effect. Clears the relevant bit of the claim tag. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 514: D9.15 Trcclaimset, Claim Tag Set Register
On writes, for each bit: Has no effect. Sets the relevant bit of the claim tag. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 515: D9.16 Trccntctlr0, Counter Control Register 0
When RLDTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. CNTTYPE, [7] Selects the resource type for the counter: Single selected resource. Boolean combined resource pair. RES0, [6:4] Reserved. RES0 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-515 reserved. Non-Confidential...
Page 516 When CNTTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0]. When CNTTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. Bit fields and details not provided in this description are architecturally defined. See the Arm ®...
Page 517: D9.17 Trccntctlr1, Counter Control Register 1
When RLDTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0]. When RLDTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. CNTTYPE, [7] Selects the resource type for the counter: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-517 reserved. Non-Confidential...
Page 518 When CNTTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0]. When CNTTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. Bit fields and details not provided in this description are architecturally defined. See the Arm ®...
Page 519: D9.18 Trccntrldvrn, Counter Reload Value Registers 0-1
Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 520: D9.19 Trccntvrn, Counter Value Registers 0-1
RES0 VALUE, [15:0] Contains the current counter value. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCCNTRLDVRn registers can be accessed through the external debug interface, offsets:...
Page 521: D9.20 Trcconfigr, Trace Configuration Register
Q elements with instruction counts are disabled. Q elements without instruction counts 0b01 are disabled. Reserved. 0b10 Q elements with and without instruction counts are enabled. 0b11 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-521 reserved. Non-Confidential...
Page 522 Controls whether load and store instructions are traced as P0 instructions. The possible values are: Load and store instructions are not traced as P0 instructions. 0b00 Load instructions are traced as P0 instructions. 0b01 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-522 reserved. Non-Confidential...
Page 523 0b11 RES1, [0] Reserved. RES1 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCCONFIGR can be accessed through the external debug interface, offset...
Page 524: D9.21 Trcdevaff0, Device Affinity Register 0
Indicates the value read in the CLUSTERIDAFF1 configuration signal. Aff0, [7:0] Affinity level 0. Lowest level affinity field. Indicates the core number in the Cortex-A76 core. The possible values are: A cluster with one core only. A cluster with two cores.
Page 525 D9 ETM registers D9.21 TRCDEVAFF0, Device Affinity Register 0 A cluster with four cores. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCDEVAFF0 can be accessed through the external debug interface, offset...
Page 526: D9.22 Trcdevaff1, Device Affinity Register 1
D9.22 TRCDEVAFF1, Device Affinity Register 1 D9.22 TRCDEVAFF1, Device Affinity Register 1 The TRCDEVAFF1 is a read-only copy of MPIDR_EL1[63:32] as seen from EL3, unaffected by VMPIDR_EL2. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-526 reserved. Non-Confidential...
Page 527: D9.23 Trcdevarch, Device Architecture Register
Architecture ID: ETMv4 component. 0x4A13 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCDEVARCH can be accessed through the external debug interface, offset...
Page 528: D9.24 Trcdevid, Device Id Register
Figure D9-22 TRCDEVID bit assignments DEVID, [31:0] RAZ. There are no component-defined capabilities. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCDEVID can be accessed through the external debug interface, offset...
Page 529: D9.25 Trcdevtype, Device Type Register
The main type of the component: Trace source. 0b0011 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCDEVTYPE can be accessed through the external debug interface, offset...
Page 530: D9.26 Trceventctl0R, Event Control 0 Register
When TYPE2 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. TYPE1, [15] Selects the resource type for trace event 1: Single selected resource. Boolean combined resource pair. RES0, [14:12] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-530 reserved. Non-Confidential...
Page 531 When TYPE0 is 0, selects a single selected resource from 0-15 defined by bits[3:0]. When TYPE0 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. Bit fields and details not provided in this description are architecturally defined. See the Arm ®...
Page 532: D9.27 Trceventctl1R, Event Control 1 Register
Event does not cause an event element. Event causes an event element. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 533: D9.28 Trcextinselr, External Input Select Register
RES0 SEL0, [4:0] Selects an event from the external input bus for External Input Resource 0. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 534: D9.29 Trcidr0, Id Register 0
Indicates how conditional results are traced: Conditional trace not supported. 0b00 NUMEVENT, [11:10] Number of events supported in the trace, minus 1: Four events supported. 0b11 RETSTACK, [9] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-534 reserved. Non-Confidential...
Page 535 0b00 RES1, [0] Reserved. RES1 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCIDR0 can be accessed through the external debug interface, offset...
Page 536: D9.30 Trcidr1, Id Register 1
REVISION, [3:0] Trace unit implementation revision number: ETM revision. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCIDR1 can be accessed through the external debug interface, offset...
Page 537: D9.31 Trcidr2, Id Register 2
Data address tracing is not implemented. 0x00 VMIDSIZE, [14:10] Virtual Machine ID size: Maximum of 32-bit Virtual Machine ID size. CIDSIZE, [9:5] Context ID size in bytes: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-537 reserved. Non-Confidential...
Page 538 IASIZE, [4:0] Instruction address size in bytes: Maximum of 64-bit address size. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCIDR2 can be accessed through the external debug interface, offset...
Page 539: D9.32 Trcidr3, Id Register 3
Indicates whether TRCSTALLCTLR is implemented: TRCSTALLCTLR is implemented. This field is used in conjunction with SYSSTALL. SYNCPR, [25] Indicates whether there is a fixed synchronization period: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-539 reserved. Non-Confidential...
Page 540 The minimum value that can be programmed in TRCCCCTLR.THRESHOLD: Instruction trace cycle counting minimum threshold is 4. 0x004 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 541: D9.33 Trcidr4, Id Register 4
Indicates the number of data value comparators available for tracing: Data value comparators not implemented. NUMACPAIRS, [3:0] Indicates the number of address comparator pairs available for tracing: 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-541 reserved. Non-Confidential...
Page 542 D9 ETM registers D9.33 TRCIDR4, ID Register 4 Four address comparator pairs are implemented. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCIDR4 can be accessed through the external debug interface, offset...
Page 543: D9.34 Trcidr5, Id Register 5
ATB trigger support: ATB trigger support implemented. TRACEIDSIZE, [21:16] Number of bits of trace ID: Seven-bit trace ID implemented. 0x07 RES0, [15:12] Reserved. RES0 NUMEXTINSEL, [11:9] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-543 reserved. Non-Confidential...
Page 544 Number of external inputs implemented: 32 external inputs implemented. 0xAD Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCIDR5 can be accessed through the external debug interface, offset...
Page 545: D9.35 Trcidr8, Id Register 8
The maximum number of P0 elements in the trace stream that can be speculative at any time. Maximum speculation depth of the instruction trace stream. Bit fields and details not provided in this description are architecturally defined. See the Arm ®...
Page 546: D9.36 Trcidr9, Id Register 9
The number of P0 right-hand keys that the trace unit can use. Number of P0 right-hand keys. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 547: D9.37 Trcidr10, Id Register 10
The number of P1 right-hand keys that the trace unit can use. Number of P1 right-hand keys. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 548: D9.38 Trcidr11, Id Register 11
The number of special P1 right-hand keys that the trace unit can use. Number of special P1 right-hand keys. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 549: D9.39 Trcidr12, Id Register 12
The number of conditional instruction right-hand keys that the trace unit can use, including normal and special keys. Number of conditional instruction right-hand keys. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 550: D9.40 Trcidr13, Id Register 13
The number of special conditional instruction right-hand keys that the trace unit can use, including normal and special keys. Number of special conditional instruction right-hand keys. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 551: D9.41 Trcimspec0, Implementation Specific Register 0
RES0 SUPPORT, [3:0] No implementation specific extensions are supported. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCIMSPEC0 can be accessed through the external debug interface, offset...
Page 552: D9.42 Trcitatbidr, Integration Atb Identification Register
When a bit is set to 1, the corresponding output pin is HIGH. The TRCITATBIDR bit values correspond to the physical state of the output pins. Bit fields and details not provided in this description are architecturally defined. See the Arm ®...
Page 553: D9.43 Trcitctrl, Integration Mode Control Register
A debug agent to perform topology detection. • SoC test software to perform integration testing. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCITCTRL can be accessed through the external debug interface, offset...
Page 554: D9.44 Trcitiatbinr, Integration Instruction Atb In Register
Returns the value of the AFVALIDMn input pin. ATREADYM, [0] Returns the value of the ATREADYMn input pin. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 555: D9.45 Trcitiatboutr, Integration Instruction Atb Out Register
Drives the AFREADYMn output pin. ATVALID, [0] Drives the ATVALIDMn output pin. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCITIATBOUTR can be accessed through the external debug interface, offset...
Page 556: D9.46 Trcitidatar, Integration Instruction Atb Data Register
Drives the ATDATAM[7] output. ATDATAM[0], [0] Drives the ATDATAM[0] output. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCITIDATAR can be accessed through the external debug interface, offset 0xEEC When a bit is set to 0, the corresponding output pin is LOW.
Page 557: D9.47 Trclar, Software Lock Access Register
Clear the software lock. 0xC5ACCE55 All other write values set the software lock. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCLAR can be accessed through the external debug interface, offset...
Page 558: D9.48 Trclsr, Software Lock Status Register
Indicates whether the software lock is implemented on this interface. Software lock is implemented on this interface. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 559: D9.49 Trccntvrn, Counter Value Registers 0-1
RES0 VALUE, [15:0] Contains the current counter value. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCCNTVRn registers can be accessed through the external debug interface, offsets:...
Page 560: D9.50 Trcoslar, Os Lock Access Register
OS Lock key value: Unlock the OS Lock. Lock the OS Lock. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCOSLAR can be accessed through the external debug interface, offset...
Page 561: D9.51 Trcoslsr, Os Lock Status Register
The value of this field is always , indicating that the OS Lock is implemented. 0b10 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 562: D9.52 Trcpdcr, Power Down Control Register
This bit is reset to 0 on a trace unit reset. RES0, [2:0] Reserved. RES0 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCPDCR can be accessed through the external debug interface, offset...
Page 563: D9.53 Trcpdsr, Power Down Status Register
If a system implementation allows the ETM trace unit to be powered off independently of the debug power domain, the system must handle accesses to the ETM trace unit appropriately. Bit fields and details not provided in this description are architecturally defined. See the Arm ®...
Page 564: D9.54 Trcpidr0, Etm Peripheral Identification Register 0
Part_0, [7:0] Least significant byte of the ETM trace unit part number. 0x0B Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCPIDR0 can be accessed through the external debug interface, offset...
Page 565: D9.55 Trcpidr1, Etm Peripheral Identification Register 1
Arm Limited. This is bits[3:0] of JEP106 ID code. Part_1, [3:0] Most significant four bits of the ETM trace unit part number. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 566: D9.56 Trcpidr2, Etm Peripheral Identification Register 2
DES_1, [2:0] Arm Limited. This is bits[6:4] of JEP106 ID code. 0b011 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCPIDR2 can be accessed through the external debug interface, offset...
Page 567: D9.57 Trcpidr3, Etm Peripheral Identification Register 3
Part minor revision. CMOD, [3:0] Not customer modified. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCPIDR3 can be accessed through the external debug interface, offset...
Page 568: D9.58 Trcpidr4, Etm Peripheral Identification Register 4
ID registers. DES_2, [3:0] Arm Limited. This is bits[3:0] of the JEP106 continuation code. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 569: D9.59 Trcpidrn, Etm Peripheral Identification Registers 5-7
TRCPIDRn, ETM Peripheral Identification Registers 5-7 No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are RES0 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-569 reserved. Non-Confidential...
Page 570: D9.60 Trcprgctlr, Programming Control Register
The ETM trace unit interface in the core is enabled, and clocks are enabled. Writes to most trace registers are ignored. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 571: D9.61 Trcrsctlrn, Resource Selection Control Registers 2-16
Selects one or more resources from the required group. One bit is provided for each resource from the group. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 572: D9.62 Trcseqevrn, Sequencer State Transition Control Registers 0-2
When F TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0]. When F TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. Bit fields and details not provided in this description are architecturally defined. See the Arm ®...
Page 573 D9 ETM registers D9.62 TRCSEQEVRn, Sequencer State Transition Control Registers 0-2 TRCSEQEVR0 0x100 TRCSEQEVR1 0x104 TRCSEQEVR2 0x108 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-573 reserved. Non-Confidential...
Page 574: D9.63 Trcseqrstevr, Sequencer Reset Control Register
When RESETTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0]. When RESETTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 575: D9.64 Trcseqstr, Sequencer State Register
State 2. 0b10 State 3. 0b11 Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCSEQSTR can be accessed through the external debug interface, offset...
Page 576: D9.65 Trcssccr0, Single-Shot Comparator Control Register 0
Selects one or more single address comparators for single-shot control. One bit is provided for each implemented single address comparator. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 577: D9.66 Trcsscsr0, Single-Shot Comparator Status Register 0
INST, [0] Instruction address comparator support: Single-shot instruction address comparisons supported. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCSSCSR0 can be accessed through the external debug interface, offset...
Page 578: D9.67 Trcstallctlr, Stall Control Register
D9 ETM registers D9.67 TRCSTALLCTLR, Stall Control Register D9.67 TRCSTALLCTLR, Stall Control Register The TRCSTALLCTLR enables the ETM trace unit to stall the Cortex-A76 core if the ETM trace unit FIFO overflows. Bit field descriptions The TRCSTALLCTLR is a 32-bit register.
Page 579: D9.68 Trcstatr, Status Register
Idle status: The ETM trace unit is not idle. The ETM trace unit is idle. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCSTATR can be accessed through the external debug interface, offset...
Page 580: D9.69 Trcsyncpr, Synchronization Period Register
• The maximum value is 20, providing a maximum synchronization period of 2 bytes. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCSYNCPR can be accessed through the external debug interface, offset...
Page 581: D9.70 Trctraceidr, Trace Id Register
TRACEID, [6:0] Trace ID value. When only instruction tracing is enabled, this provides the trace ID. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 582: D9.71 Trctsctlr, Global Timestamp Control Register
RES0 SEL, [3:1] Identifies the resource selector to use. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile. The TRCTSCTLR can be accessed through the external debug interface, offset...
Page 583: D9.72 Trcvictlr, Viewinst Main Control Register
Bit[16] Exception level 0. Bit[17] Exception level 1. Bit[18] RAZ/WI. Instruction tracing is not implemented for exception level 2. Bit[19] Exception level 3. RES0, [15:12] Reserved. RES0 TRCERR, [11] 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-583 reserved. Non-Confidential...
Page 584 When TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0]. When TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. Bit fields and details not provided in this description are architecturally defined. See the Arm ®...
Page 585: D9.73 Trcviiectlr, Viewinst Include-Exclude Control Register
One bit is provided for each implemented Address Range Comparator. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 586: D9.74 Trcvissctlr, Viewinst Start-Stop Control Register
Defines the single address comparators to start trace with the ViewInst Start/Stop control. One bit is provided for each implemented single address comparator. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 587: D9.75 Trcvmidcvr0, Vmid Comparator Value Register 0
The TRCVMIDCVR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x640 Usage constraints Accepts writes only when the trace unit is disabled. Configurations Available in all configurations. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights D9-587 reserved. Non-Confidential...
Page 588: D9.76 Trcvmidcctlr0, Virtual Context Identifier Comparator Control Register 0
The trace unit ignores the relevant byte in TRCVMIDCVR0 when it performs the Virtual context ID comparison. Bit fields and details not provided in this description are architecturally defined. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Page 589 Part E Appendices...
Page 591 Appendix A Cortex -A76 Core AArch32 unpredictable behaviors ® This appendix describes the cases in which the Cortex-A76 core implementation diverges from the preferred behavior described in Armv8 AArch32 behaviors. UNPREDICTABLE It contains the following sections: • A.1 Use of R15 by Instruction on page Appx-A-592.
Page 592 In this case, if the instruction specifies Writeback, then the load or store is performed without Writeback. The Cortex-A76 core does not implement a Read 0 or Ignore Write policy on use of R15 UNPREDICTABLE by instruction.
Page 593 A.2 Load/Store accesses crossing page boundaries Load/Store accesses crossing page boundaries The Cortex-A76 core implements a set of behaviors for load or store accesses that cross page boundaries. Crossing a page boundary with different memory types or shareability attributes The Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile, states that a ®...
Page 594 -A76 Core AArch32 unpredictable behaviors ® A.3 Armv8 Debug UNPREDICTABLE behaviors Armv8 Debug UNPREDICTABLE behaviors This section describes the behavior that the Cortex-A76 core implements when: • A topic has multiple options. • The behavior differs from either or both of the Options and Preferences behaviors.
Page 595 Writes set the accessed register(s) to UNKNOWN > External debug write to register that is being reset The core behaves as indicated in the sole Preference: • Takes reset value. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights Appx-A-595 reserved. Non-Confidential...
Page 596 Clearing the clear-after-read EDPRSR bits when The core behaves as indicated in the sole Preference: Core power domain is on, and • Bits are not cleared to zero. DoubleLockStatus() is TRUE 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights Appx-A-596 reserved. Non-Confidential...
Page 597 CRC32 or CRC32C instruction The core implements the following option: with cond!=1110 in the A1 • Executed unconditionally. encoding. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights Appx-A-597 reserved. Non-Confidential...
Page 598 A Cortex -A76 Core AArch32 unpredictable behaviors ® A.4 Other UNPREDICTABLE behaviors 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. Appx-A-598 Non-Confidential...
Page 599 Appendix B Revisions This appendix describes the technical changes between released issues of this book. It contains the following section: • B.1 Revisions on page Appx-B-600. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights Appx-B-599 reserved. Non-Confidential...
Page 600 D9.1 ETM register summary on page D9-495 r1p0 Updated reset value for TRCIDR1 register. D9.30 TRCIDR1, ID Register 1 on page D9-536 r1p0 Updated bits [3:0] of TRCIDR1 register. 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights Appx-B-600 reserved. Non-Confidential...
Page 601 D9.1 ETM register summary on page D9-495 r3p0 Updated reset value for TRCIDR1. r3p0 Added SSBS field to ID_AA64PFR1_EL1. B2.62 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1 on page B2-229 100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights Appx-B-601 reserved. Non-Confidential...

ARM Cortex-A76 Core Technical Reference Manual

Preface

Part a Functional Description

Chapter A1

Introduction

Chapter A2

Technical Overview

Chapter A3

Clocks, Resets, and Input Synchronization

Chapter A4

Power Management

Chapter A5

Memory Management Unit

Chapter A6

Level 1 Memory System

Chapter A7

Level 2 Memory System

Reliability, Availability, and Serviceability (RAS)

Chapter A9

Generic Interrupt Controller CPU Interface

Chapter A10

Advanced SIMD and Floating-Point Support

Part B

Chapter B1

Aarch32 System Registers

Chapter B2

Aarch64 System Registers

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Summary of Contents for ARM Cortex-A76 Core