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6.7
Memory attributes and types
Memory
Shared or
type
Non-shared
attribute
Strongly
-
Ordered
Device
Shared
Non-shared
Normal
Shared
Non-shared
6.7.1
Normal memory attribute
ARM DDI 0301H
ID012310
The processor provides a set of memory attributes that have characteristics that are suited to
particular devices, including memory devices, that can be contained in the memory map. The
ordering of accesses for regions of memory is also defined by the memory attributes. There are
three mutually exclusive main memory type attributes:
•
Strongly Ordered
•
Device
•
Normal.
These are used to describe the memory regions. The marking of the same memory locations as
having two different attributes in the MMU, for example using synonyms in a virtual to physical
address mapping, results in Unpredictable behavior but this does not break security. Table 6-9
lists a summary of the memory attributes.
Other attributes
-
-
-
Noncacheable/
Write-Through
Cacheable/
Write-Back Cacheable
Noncacheable/
Write-Through
Cacheable/
Write-Back Cacheable
The Normal memory attribute is defined on a per-page basis in the MMU and provides memory
access orderings that are suitable for normal memory. This type of memory stores information
without side effects. Normal memory can be writable or read-only. For writable normal memory,
unless there is a change to the physical address mapping:
•
a load from a specific location returns the most recently stored data at that location for the
same processor
•
two loads from a specific location, without a store in between, return the same data for
each load.
For read-only normal memory:
•
two loads from a specific location return the same data for each load.
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Non-Confidential, Unrestricted Access
Description
All memory accesses to Strongly Ordered memory occur in
program order. Some backwards compatibility constraints
exist with ARMv5 instructions that change the CPSR interrupt
masks. See Strongly Ordered memory attribute on page 6-23.
All Strongly Ordered accesses are assumed to be shared.
Designed to handle memory-mapped peripherals that are
shared by several processors.
Designed to handle memory-mapped peripherals that are used
only by a single processor.
Designed to handle normal memory that is shared between
several processors.
Designed to handle normal memory that is used only by a
single processor.
Memory Management Unit
Table 6-9 Memory attributes
6-20
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